Searched refs:PLLR (Results 1 – 6 of 6) sorted by relevance
| /loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/ |
| D | stm32l4xx_ll_utils.c | 391 UTILS_PLLInitStruct->PLLR); in LL_PLL_ConfigSystemClock_MSI()
469 UTILS_PLLInitStruct->PLLR); in LL_PLL_ConfigSystemClock_HSI()
565 UTILS_PLLInitStruct->PLLR); in LL_PLL_ConfigSystemClock_HSE()
756 assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR)); in UTILS_GetPLLOutputFrequency()
768 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U); in UTILS_GetPLLOutputFrequency()
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| D | stm32l4xx_hal_rcc.c | 902 assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); in HAL_RCC_OscConfig()
925 RCC_OscInitStruct->PLL.PLLR); in HAL_RCC_OscConfig()
1592 …RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos)… in HAL_RCC_GetOscConfig()
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| /loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/ |
| D | stm32l4xx_ll_utils.h | 125 uint32_t PLLR; /*!< Division for the main system clock. member
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| D | stm32l4xx_ll_rcc.h | 3813 …LINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) in LL_RCC_PLL_ConfigDomain_SYS() argument
3816 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR); in LL_RCC_PLL_ConfigDomain_SYS()
4550 … void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) in LL_RCC_PLLSAI1_ConfigDomain_ADC() argument
4554 PLLM | (PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | PLLR); in LL_RCC_PLLSAI1_ConfigDomain_ADC()
4589 … void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) in LL_RCC_PLLSAI1_ConfigDomain_ADC() argument
4592 … RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR); in LL_RCC_PLLSAI1_ConfigDomain_ADC()
5094 …2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) in LL_RCC_PLLSAI2_ConfigDomain_LTDC() argument
5098 (PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | PLLR | PLLM); in LL_RCC_PLLSAI2_ConfigDomain_LTDC()
5134 … void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) in LL_RCC_PLLSAI2_ConfigDomain_ADC() argument
5137 … RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR); in LL_RCC_PLLSAI2_ConfigDomain_ADC()
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| D | stm32l4xx_hal_rcc.h | 86 uint32_t PLLR; /*!< PLLR: Division for the main system clock. member
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| /loramac-node-2.7.6/src/boards/NucleoL476/ |
| D | board.c | 374 RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; in SystemClockConfig()
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