Searched refs:PATT (Results 1 – 4 of 4) sorted by relevance
7334 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; in hri_tcc_set_PATT_PGE0_bit()7341 tmp = ((Tcc *)hw)->PATT.reg; in hri_tcc_get_PATT_PGE0_bit()7351 tmp = ((Tcc *)hw)->PATT.reg; in hri_tcc_write_PATT_PGE0_bit()7354 ((Tcc *)hw)->PATT.reg = tmp; in hri_tcc_write_PATT_PGE0_bit()7362 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; in hri_tcc_clear_PATT_PGE0_bit()7370 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; in hri_tcc_toggle_PATT_PGE0_bit()7378 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; in hri_tcc_set_PATT_PGE1_bit()7385 tmp = ((Tcc *)hw)->PATT.reg; in hri_tcc_get_PATT_PGE1_bit()7395 tmp = ((Tcc *)hw)->PATT.reg; in hri_tcc_write_PATT_PGE1_bit()7398 ((Tcc *)hw)->PATT.reg = tmp; in hri_tcc_write_PATT_PGE1_bit()[all …]
652 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | in FMC_NAND_AttributeSpace_Timing_Init()682 WRITE_REG(Device->PATT, 0xFCFCFCFC); in FMC_NAND_DeInit()
250 uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ member1686 __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ member
539 …__IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: … member
