Home
last modified time | relevance | path

Searched refs:MODIFY_REG (Results 1 – 25 of 196) sorted by relevance

12345678

/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_ll_tim.c353 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); in LL_TIM_Init()
359 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); in LL_TIM_Init()
747 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); in LL_TIM_BDTR_Init()
748 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); in LL_TIM_BDTR_Init()
749 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); in LL_TIM_BDTR_Init()
750 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); in LL_TIM_BDTR_Init()
751 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); in LL_TIM_BDTR_Init()
752 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); in LL_TIM_BDTR_Init()
753 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
754 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
[all …]
Dstm32l4xx_hal_opamp_ex.c151 MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); in HAL_OPAMPEx_SelfCalibrateAll()
152 MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); in HAL_OPAMPEx_SelfCalibrateAll()
199 MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1); in HAL_OPAMPEx_SelfCalibrateAll()
200 MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2); in HAL_OPAMPEx_SelfCalibrateAll()
235 MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1); in HAL_OPAMPEx_SelfCalibrateAll()
236 MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2); in HAL_OPAMPEx_SelfCalibrateAll()
247 MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1); in HAL_OPAMPEx_SelfCalibrateAll()
254 MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2); in HAL_OPAMPEx_SelfCalibrateAll()
271 …MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1<<OPAMP_INPUT_NONINVER… in HAL_OPAMPEx_SelfCalibrateAll()
272 …MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2<<OPAMP_INPUT_NONINVER… in HAL_OPAMPEx_SelfCalibrateAll()
[all …]
Dstm32l4xx_hal_opamp.c384 MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_PGA, \ in HAL_OPAMP_Init()
396 MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_FOLLOWER, \ in HAL_OPAMP_Init()
405 MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_STANDALONE, \ in HAL_OPAMP_Init()
424 … MODIFY_REG(hopamp->Instance->OTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr); in HAL_OPAMP_Init()
433 …MODIFY_REG(hopamp->Instance->LPOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr); in HAL_OPAMP_Init()
440 MODIFY_REG(OPAMP1->CSR, OPAMP1_CSR_OPARANGE, hopamp->Init.PowerSupplyRange); in HAL_OPAMP_Init()
483 MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_BITS, OPAMP_CSR_RESET_VALUE); in HAL_OPAMP_DeInit()
694 MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE); in HAL_OPAMP_SelfCalibrate()
727 MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen); in HAL_OPAMP_SelfCalibrate()
751 MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen); in HAL_OPAMP_SelfCalibrate()
[all …]
Dstm32l4xx_hal_flash_ramfunc.c190 …MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_S… in HAL_FLASHEx_OB_DBankConfig()
198 …MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_S… in HAL_FLASHEx_OB_DBankConfig()
206 …MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_S… in HAL_FLASHEx_OB_DBankConfig()
214 …MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_S… in HAL_FLASHEx_OB_DBankConfig()
218 MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig); in HAL_FLASHEx_OB_DBankConfig()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_dma2d.h551 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP); in LL_DMA2D_Suspend()
588 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT); in LL_DMA2D_Abort()
621 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode); in LL_DMA2D_SetMode()
657 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode); in LL_DMA2D_SetOutputColorMode()
687 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode); in LL_DMA2D_SetOutputRBSwapMode()
714 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode); in LL_DMA2D_SetOutputAlphaInvMode()
743 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode); in LL_DMA2D_SetOutputSwapMode()
772 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode); in LL_DMA2D_SetLineOffsetMode()
802 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset); in LL_DMA2D_SetLineOffset()
829 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos)); in LL_DMA2D_SetNbrOfPixelsPerLines()
[all …]
Dstm32l4xx_ll_rcc.h2208 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); in LL_RCC_HSI_SetCalibTrimming()
2332 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); in LL_RCC_LSE_SetDriveCapability()
2474 MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, LSI_PREDIV); in LL_RCC_LSI_SetPrediv()
2597 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range); in LL_RCC_MSI_SetRange()
2634 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range); in LL_RCC_MSI_SetRangeAfterStandby()
2672 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); in LL_RCC_MSI_SetCalibTrimming()
2723 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); in LL_RCC_LSCO_SetSource()
2758 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); in LL_RCC_SetSysClkSource()
2792 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); in LL_RCC_SetAHBPrescaler()
2808 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); in LL_RCC_SetAPB1Prescaler()
[all …]
Dstm32l4xx_ll_opamp.h394 MODIFY_REG(OPAMP1->CSR, OPAMP1_CSR_OPARANGE, PowerRange); in LL_OPAMP_SetCommonPowerRange()
433 MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_OPALPM, (PowerMode & OPAMP_POWERMODE_CSR_BIT_MASK)); in LL_OPAMP_SetPowerMode()
473 MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALON, Mode); in LL_OPAMP_SetMode()
513 MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_OPAMODE | OPAMP_CSR_CALON, FunctionalMode); in LL_OPAMP_SetFunctionalMode()
546 MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN, PGAGain); in LL_OPAMP_SetPGAGain()
585 MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSEL, InputNonInverting); in LL_OPAMP_SetInputNonInverting()
617 MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VMSEL, InputInverting); in LL_OPAMP_SetInputInverting()
672 MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_USERTRIM, TrimmingMode); in LL_OPAMP_SetTrimmingMode()
704 MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALSEL, (TransistorsDiffPair & OPAMP_TRIMMING_SELECT_MASK)); in LL_OPAMP_SetCalibrationSelection()
766 MODIFY_REG(*preg, in LL_OPAMP_SetTrimmingValue()
Dstm32l4xx_ll_comp.h371 MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_WINMODE, WindowMode); in LL_COMP_SetCommonWindowMode()
410 MODIFY_REG(COMPx->CSR, COMP_CSR_PWRMODE, PowerMode); in LL_COMP_SetPowerMode()
482 MODIFY_REG(COMPx->CSR, in LL_COMP_ConfigInputs()
486 MODIFY_REG(COMPx->CSR, in LL_COMP_ConfigInputs()
509 MODIFY_REG(COMPx->CSR, COMP_CSR_INPSEL, InputPlus); in LL_COMP_SetInputPlus()
571 …MODIFY_REG(COMPx->CSR, COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN, Inpu… in LL_COMP_SetInputMinus()
573 MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN, InputMinus); in LL_COMP_SetInputMinus()
623 MODIFY_REG(COMPx->CSR, COMP_CSR_HYST, InputHysteresis); in LL_COMP_SetInputHysteresis()
660 MODIFY_REG(COMPx->CSR, COMP_CSR_POLARITY, OutputPolarity); in LL_COMP_SetOutputPolarity()
701 MODIFY_REG(COMPx->CSR, COMP_CSR_BLANKING, BlankingSource); in LL_COMP_SetOutputBlankingSource()
Dstm32l4xx_ll_dac.h615 MODIFY_REG(DACx->CR, DAC_CR_HFSEL, HighFreqMode); in LL_DAC_SetHighFrequencyMode()
656 MODIFY_REG(DACx->CR, in LL_DAC_SetMode()
696 MODIFY_REG(DACx->CCR, in LL_DAC_SetTrimmingValue()
752 MODIFY_REG(DACx->CR, in LL_DAC_SetTriggerSource()
814 MODIFY_REG(DACx->CR, in LL_DAC_SetWaveAutoGeneration()
877 MODIFY_REG(DACx->CR, in LL_DAC_SetWaveNoiseLFSR()
949 MODIFY_REG(DACx->CR, in LL_DAC_SetWaveTriangleAmplitude()
1036 MODIFY_REG(DACx->MCR, in LL_DAC_ConfigOutput()
1066 MODIFY_REG(DACx->MCR, in LL_DAC_SetOutputMode()
1115 MODIFY_REG(DACx->MCR, in LL_DAC_SetOutputBuffer()
[all …]
Dstm32l4xx_hal_rcc_ex.h989 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_…
1006 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PL…
1026 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI…
1031 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_P…
1048 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI…
1063 …MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI…
1218 …MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_…
1235 …MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_P…
1252 …MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_P…
1269 …MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q, (((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI…
[all …]
Dstm32l4xx_ll_rtc.h908 MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); in LL_RTC_SetHourFormat()
938 MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput); in LL_RTC_SetAlarmOutEvent()
968 MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output); in LL_RTC_SetAlarmOutputType()
1025 MODIFY_REG(RTCx->OR, RTC_OR_ALARMOUTTYPE, Output); in LL_RTC_SetAlarmOutputType()
1082 MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); in LL_RTC_SetOutputPolarity()
1167 MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos); in LL_RTC_SetAsynchPrescaler()
1179 MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler); in LL_RTC_SetSynchPrescaler()
1378 MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); in LL_RTC_TIME_SetFormat()
1411 MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), in LL_RTC_TIME_SetHour()
1446 MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU), in LL_RTC_TIME_SetMinute()
[all …]
Dstm32l4xx_ll_spi.h416 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); in LL_SPI_SetMode()
445 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); in LL_SPI_SetStandard()
474 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); in LL_SPI_SetClockPhase()
503 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); in LL_SPI_SetClockPolarity()
537 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); in LL_SPI_SetBaudRatePrescaler()
571 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); in LL_SPI_SetTransferBitOrder()
604 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); in LL_SPI_SetTransferDirection()
646 MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); in LL_SPI_SetDataWidth()
684 MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); in LL_SPI_SetRxFIFOThreshold()
756 MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); in LL_SPI_SetCRCWidth()
[all …]
Dstm32l4xx_ll_crs.h307 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); in LL_CRS_SetHSI48SmoothTrimming()
330 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); in LL_CRS_SetReloadCounter()
352 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); in LL_CRS_SetFreqErrorLimit()
381 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); in LL_CRS_SetSyncDivider()
413 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); in LL_CRS_SetSyncSignalSource()
439 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); in LL_CRS_SetSyncPolarity()
474 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); in LL_CRS_ConfigSynchronization()
475 MODIFY_REG(CRS->CFGR, in LL_CRS_ConfigSynchronization()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_rtc.h816 MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); in LL_RTC_SetHourFormat()
846 MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput); in LL_RTC_SetAlarmOutEvent()
876 MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE, Output); in LL_RTC_SetAlarmOutputType()
932 MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); in LL_RTC_SetOutputPolarity()
1019 MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos); in LL_RTC_SetAsynchPrescaler()
1031 MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler); in LL_RTC_SetSynchPrescaler()
1100 MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); in LL_RTC_TIME_SetFormat()
1133 MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), in LL_RTC_TIME_SetHour()
1171 MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU), in LL_RTC_TIME_SetMinute()
1209 MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), in LL_RTC_TIME_SetSecond()
[all …]
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_ll_tim.c275 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); in LL_TIM_Init()
281 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); in LL_TIM_Init()
536 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); in OC1Config()
539 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); in OC1Config()
542 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
595 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); in OC2Config()
598 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); in OC2Config()
601 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
654 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
657 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); in OC3Config()
[all …]
Dstm32l1xx_hal_adc_ex.c660 MODIFY_REG(hadc->Instance->JSQR , in HAL_ADCEx_InjectedConfigChannel()
689 MODIFY_REG(hadc->Instance->JSQR , in HAL_ADCEx_InjectedConfigChannel()
704 MODIFY_REG(hadc->Instance->JSQR , in HAL_ADCEx_InjectedConfigChannel()
723 MODIFY_REG(hadc->Instance->CR2 , in HAL_ADCEx_InjectedConfigChannel()
731 MODIFY_REG(hadc->Instance->CR2, in HAL_ADCEx_InjectedConfigChannel()
786 MODIFY_REG(hadc->Instance->SMPR3, in HAL_ADCEx_InjectedConfigChannel()
793 MODIFY_REG(hadc->Instance->SMPR2, in HAL_ADCEx_InjectedConfigChannel()
801 MODIFY_REG(hadc->Instance->SMPR1, in HAL_ADCEx_InjectedConfigChannel()
817 MODIFY_REG(hadc->Instance->JOFR1, in HAL_ADCEx_InjectedConfigChannel()
823 MODIFY_REG(hadc->Instance->JOFR2, in HAL_ADCEx_InjectedConfigChannel()
[all …]
Dstm32l1xx_hal_opamp_ex.c234 MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_L_ALL, in HAL_OPAMPEx_SelfCalibrateAll()
252 MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H_ALL, in HAL_OPAMPEx_SelfCalibrateAll()
276 …MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM… in HAL_OPAMPEx_SelfCalibrateAll()
279 …MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM… in HAL_OPAMPEx_SelfCalibrateAll()
282 …MODIFY_REG(*tmp_opamp3_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, OPAMP_TRIM… in HAL_OPAMPEx_SelfCalibrateAll()
348 …MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM… in HAL_OPAMPEx_SelfCalibrateAll()
356 …MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM… in HAL_OPAMPEx_SelfCalibrateAll()
364 …MODIFY_REG(*tmp_opamp3_reg_trimming, OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, OPAMP_TRIM… in HAL_OPAMPEx_SelfCalibrateAll()
575 MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_L_ALL, in HAL_OPAMPEx_SelfCalibrateAll()
591 MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H_ALL, in HAL_OPAMPEx_SelfCalibrateAll()
[all …]
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
Dstm32l0xx_ll_tim.c252 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); in LL_TIM_Init()
258 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); in LL_TIM_Init()
514 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); in OC1Config()
517 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); in OC1Config()
520 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
573 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); in OC2Config()
576 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); in OC2Config()
579 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
632 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
635 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); in OC3Config()
[all …]
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_ll_rtc.h807 MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); in LL_RTC_SetHourFormat()
837 MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput); in LL_RTC_SetAlarmOutEvent()
867 MODIFY_REG(RTCx->OR, RTC_OR_ALARMOUTTYPE, Output); in LL_RTC_SetAlarmOutputType()
923 MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); in LL_RTC_SetOutputPolarity()
1008 MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_POSITION_PRER_PREDIV_A); in LL_RTC_SetAsynchPrescaler()
1020 MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler); in LL_RTC_SetSynchPrescaler()
1111 MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); in LL_RTC_TIME_SetFormat()
1144 MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), in LL_RTC_TIME_SetHour()
1182 MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU), in LL_RTC_TIME_SetMinute()
1220 MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), in LL_RTC_TIME_SetSecond()
[all …]
Dstm32l0xx_ll_adc.h1671 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock); in LL_ADC_SetCommonClock()
1721 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_LFMEN, Resolution); in LL_ADC_SetCommonFrequencyMode()
1780 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VLCDEN, PathInternal); in LL_ADC_SetCommonPathInternalCh()
1782 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal); in LL_ADC_SetCommonPathInternalCh()
1847 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); in LL_ADC_SetClock()
1891 MODIFY_REG(ADCx->CALFACT, in LL_ADC_SetCalibrationFactor()
1929 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution); in LL_ADC_SetResolution()
1966 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment); in LL_ADC_SetDataAlignment()
2036 MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode); in LL_ADC_SetLowPowerMode()
2131 MODIFY_REG(ADCx->SMPR, ADC_SMPR_SMP, SamplingTime); in LL_ADC_SetSamplingTimeCommonChannels()
[all …]
Dstm32l0xx_ll_usart.h686 MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); in LL_USART_SetTransferDirection()
721 MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); in LL_USART_SetParity()
750 MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); in LL_USART_SetWakeUpMethod()
779 MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); in LL_USART_SetDataWidth()
841 MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); in LL_USART_SetOverSampling()
870 MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); in LL_USART_SetLastClkPulseOutput()
902 MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); in LL_USART_SetClockPhase()
933 MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); in LL_USART_SetClockPolarity()
976 …MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPO… in LL_USART_ConfigClock()
1031 MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); in LL_USART_SetStopBitsLength()
[all …]
Dstm32l0xx_ll_comp.h296 MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_COMP1WM, WindowMode); in LL_COMP_SetCommonWindowMode()
335 MODIFY_REG(COMPx->CSR, COMP_CSR_COMP2SPEED, PowerMode); in LL_COMP_SetPowerMode()
399 MODIFY_REG(COMPx->CSR, in LL_COMP_ConfigInputs()
424 MODIFY_REG(COMPx->CSR, COMP_CSR_COMP2INPSEL, InputPlus); in LL_COMP_SetInputPlus()
477 MODIFY_REG(COMPx->CSR, COMP_CSR_COMP2INNSEL, InputMinus); in LL_COMP_SetInputMinus()
530 …MODIFY_REG(COMPx->CSR, (COMP_CSR_COMP1LPTIM1IN1 | COMP_CSR_COMP2LPTIM1IN1 | COMP_CSR_COMP2LPTIM1IN… in LL_COMP_SetOutputLPTIM()
563 MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxPOLARITY, OutputPolarity); in LL_COMP_SetOutputPolarity()
Dstm32l0xx_ll_lptim.h378 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode); in LL_LPTIM_StartCounter()
393 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode); in LL_LPTIM_SetUpdateMode()
424 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload); in LL_LPTIM_SetAutoReload()
451 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue); in LL_LPTIM_SetCompare()
492 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode); in LL_LPTIM_SetCounterMode()
527 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity); in LL_LPTIM_ConfigOutput()
541 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform); in LL_LPTIM_SetWaveform()
568 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity); in LL_LPTIM_SetPolarity()
606 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler); in LL_LPTIM_SetPrescaler()
722 …MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filt… in LL_LPTIM_ConfigTrigger()
[all …]
Dstm32l0xx_ll_crs.h317 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM); in LL_CRS_SetHSI48SmoothTrimming()
340 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); in LL_CRS_SetReloadCounter()
362 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM); in LL_CRS_SetFreqErrorLimit()
391 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); in LL_CRS_SetSyncDivider()
423 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); in LL_CRS_SetSyncSignalSource()
449 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); in LL_CRS_SetSyncPolarity()
484 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); in LL_CRS_ConfigSynchronization()
485 MODIFY_REG(CRS->CFGR, in LL_CRS_ConfigSynchronization()
Dstm32l0xx_ll_rcc.h782 MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div); in LL_RCC_SetRTC_HSEPrescaler()
925 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_POSITION_HSITRIM); in LL_RCC_HSI_SetCalibTrimming()
1083 MODIFY_REG(RCC->CSR, RCC_CSR_LSEDRV, LSEDrive); in LL_RCC_LSE_SetDriveCapability()
1233 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range); in LL_RCC_MSI_SetRange()
1274 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_POSITION_MSITRIM); in LL_RCC_MSI_SetCalibTrimming()
1307 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); in LL_RCC_SetSysClkSource()
1341 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); in LL_RCC_SetAHBPrescaler()
1357 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); in LL_RCC_SetAPB1Prescaler()
1373 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); in LL_RCC_SetAPB2Prescaler()
1435 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); in LL_RCC_SetClkAfterWakeFromStop()
[all …]

12345678