Searched refs:IMR1 (Results 1 – 10 of 10) sorted by relevance
281 temp = EXTI->IMR1; in HAL_GPIO_Init()287 EXTI->IMR1 = temp; in HAL_GPIO_Init()377 EXTI->IMR1 &= ~(iocurrent); in HAL_GPIO_DeInit()
239 regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); in HAL_EXTI_SetConfigLine()311 regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); in HAL_EXTI_GetConfigLine()411 regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); in HAL_EXTI_ClearConfigLine()
99 LL_EXTI_WriteReg(IMR1, 0xFF820000U); in LL_EXTI_DeInit()
324 SET_BIT(EXTI->IMR1, ExtiLine); in LL_EXTI_EnableIT_0_31()396 CLEAR_BIT(EXTI->IMR1, ExtiLine); in LL_EXTI_DisableIT_0_31()469 return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); in LL_EXTI_IsEnabledIT_0_31()
240 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)246 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
261 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE262 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)279 #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI…280 #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EX…
682 #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)688 #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVE…1159 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_TIME…1165 #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TI…
747 #define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)753 #define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
2120 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)2126 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
450 …__IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ member
