1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_flash.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L4xx_HAL_FLASH_H 38 #define __STM32L4xx_HAL_FLASH_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l4xx_hal_def.h" 46 47 /** @addtogroup STM32L4xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup FLASH 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup FLASH_Exported_Types FLASH Exported Types 57 * @{ 58 */ 59 60 /** 61 * @brief FLASH Erase structure definition 62 */ 63 typedef struct 64 { 65 uint32_t TypeErase; /*!< Mass erase or page erase. 66 This parameter can be a value of @ref FLASH_Type_Erase */ 67 uint32_t Banks; /*!< Select bank to erase. 68 This parameter must be a value of @ref FLASH_Banks 69 (FLASH_BANK_BOTH should be used only for mass erase) */ 70 uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled 71 This parameter must be a value between 0 and (max number of pages in the bank - 1) 72 (eg : 255 for 1MB dual bank) */ 73 uint32_t NbPages; /*!< Number of pages to be erased. 74 This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ 75 } FLASH_EraseInitTypeDef; 76 77 /** 78 * @brief FLASH Option Bytes Program structure definition 79 */ 80 typedef struct 81 { 82 uint32_t OptionType; /*!< Option byte to be configured. 83 This parameter can be a combination of the values of @ref FLASH_OB_Type */ 84 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). 85 Only one WRP area could be programmed at the same time. 86 This parameter can be value of @ref FLASH_OB_WRP_Area */ 87 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). 88 This parameter must be a value between 0 and (max number of pages in the bank - 1) 89 (eg : 25 for 1MB dual bank) */ 90 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). 91 This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */ 92 uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP). 93 This parameter can be a value of @ref FLASH_OB_Read_Protection */ 94 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 95 This parameter can be a combination of @ref FLASH_OB_USER_Type */ 96 uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). 97 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, 98 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, 99 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 100 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 101 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, 102 @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, 103 @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */ 104 uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). 105 This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) 106 and @ref FLASH_OB_PCROP_RDP */ 107 uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). 108 This parameter must be a value between begin and end of bank 109 => Be careful of the bank swapping for the address */ 110 uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). 111 This parameter must be a value between PCROP Start address and end of bank */ 112 } FLASH_OBProgramInitTypeDef; 113 114 /** 115 * @brief FLASH Procedure structure definition 116 */ 117 typedef enum 118 { 119 FLASH_PROC_NONE = 0, 120 FLASH_PROC_PAGE_ERASE, 121 FLASH_PROC_MASS_ERASE, 122 FLASH_PROC_PROGRAM, 123 FLASH_PROC_PROGRAM_LAST 124 } FLASH_ProcedureTypeDef; 125 126 /** 127 * @brief FLASH Cache structure definition 128 */ 129 typedef enum 130 { 131 FLASH_CACHE_DISABLED = 0, 132 FLASH_CACHE_ICACHE_ENABLED, 133 FLASH_CACHE_DCACHE_ENABLED, 134 FLASH_CACHE_ICACHE_DCACHE_ENABLED 135 } FLASH_CacheTypeDef; 136 137 /** 138 * @brief FLASH handle Structure definition 139 */ 140 typedef struct 141 { 142 HAL_LockTypeDef Lock; /* FLASH locking object */ 143 __IO uint32_t ErrorCode; /* FLASH error code */ 144 __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ 145 __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */ 146 __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */ 147 __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ 148 __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ 149 __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */ 150 }FLASH_ProcessTypeDef; 151 152 /** 153 * @} 154 */ 155 156 /* Exported constants --------------------------------------------------------*/ 157 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 158 * @{ 159 */ 160 161 /** @defgroup FLASH_Error FLASH Error 162 * @{ 163 */ 164 #define HAL_FLASH_ERROR_NONE 0x00000000U 165 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR 166 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR 167 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR 168 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR 169 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR 170 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR 171 #define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR 172 #define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR 173 #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR 174 #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR 175 #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD 176 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ 177 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ 178 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 179 #define HAL_FLASH_ERROR_PEMPTY FLASH_FLAG_PEMPTY 180 #endif 181 /** 182 * @} 183 */ 184 185 /** @defgroup FLASH_Type_Erase FLASH Erase Type 186 * @{ 187 */ 188 #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/ 189 #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/ 190 /** 191 * @} 192 */ 193 194 /** @defgroup FLASH_Banks FLASH Banks 195 * @{ 196 */ 197 #define FLASH_BANK_1 ((uint32_t)0x01) /*!< Bank 1 */ 198 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 199 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 200 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 201 #define FLASH_BANK_2 ((uint32_t)0x02) /*!< Bank 2 */ 202 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ 203 #else 204 #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1)) /*!< Bank 1 */ 205 #endif 206 /** 207 * @} 208 */ 209 210 211 /** @defgroup FLASH_Type_Program FLASH Program Type 212 * @{ 213 */ 214 #define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x00) /*!<Program a double-word (64-bit) at a specified address.*/ 215 #define FLASH_TYPEPROGRAM_FAST ((uint32_t)0x01) /*!<Fast program a 32 row double-word (64-bit) at a specified address. 216 And another 32 row double-word (64-bit) will be programmed */ 217 #define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02) /*!<Fast program a 32 row double-word (64-bit) at a specified address. 218 And this is the last 32 row double-word (64-bit) programmed */ 219 /** 220 * @} 221 */ 222 223 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type 224 * @{ 225 */ 226 #define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */ 227 #define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */ 228 #define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */ 229 #define OPTIONBYTE_PCROP ((uint32_t)0x08) /*!< PCROP option byte configuration */ 230 /** 231 * @} 232 */ 233 234 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area 235 * @{ 236 */ 237 #define OB_WRPAREA_BANK1_AREAA ((uint32_t)0x00) /*!< Flash Bank 1 Area A */ 238 #define OB_WRPAREA_BANK1_AREAB ((uint32_t)0x01) /*!< Flash Bank 1 Area B */ 239 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 240 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 241 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 242 #define OB_WRPAREA_BANK2_AREAA ((uint32_t)0x02) /*!< Flash Bank 2 Area A */ 243 #define OB_WRPAREA_BANK2_AREAB ((uint32_t)0x04) /*!< Flash Bank 2 Area B */ 244 #endif 245 /** 246 * @} 247 */ 248 249 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection 250 * @{ 251 */ 252 #define OB_RDP_LEVEL_0 ((uint32_t)0xAA) 253 #define OB_RDP_LEVEL_1 ((uint32_t)0xBB) 254 #define OB_RDP_LEVEL_2 ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2 255 it's no more possible to go back to level 1 or 0 */ 256 /** 257 * @} 258 */ 259 260 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type 261 * @{ 262 */ 263 #define OB_USER_BOR_LEV ((uint32_t)0x0001) /*!< BOR reset Level */ 264 #define OB_USER_nRST_STOP ((uint32_t)0x0002) /*!< Reset generated when entering the stop mode */ 265 #define OB_USER_nRST_STDBY ((uint32_t)0x0004) /*!< Reset generated when entering the standby mode */ 266 #define OB_USER_IWDG_SW ((uint32_t)0x0008) /*!< Independent watchdog selection */ 267 #define OB_USER_IWDG_STOP ((uint32_t)0x0010) /*!< Independent watchdog counter freeze in stop mode */ 268 #define OB_USER_IWDG_STDBY ((uint32_t)0x0020) /*!< Independent watchdog counter freeze in standby mode */ 269 #define OB_USER_WWDG_SW ((uint32_t)0x0040) /*!< Window watchdog selection */ 270 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 271 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 272 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 273 #define OB_USER_BFB2 ((uint32_t)0x0080) /*!< Dual-bank boot */ 274 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 275 #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 1MB or 512kB Flash memory devices */ 276 #else 277 #define OB_USER_DUALBANK ((uint32_t)0x0100) /*!< Dual-Bank on 512KB or 256KB Flash memory devices */ 278 #endif 279 #endif 280 #define OB_USER_nBOOT1 ((uint32_t)0x0200) /*!< Boot configuration */ 281 #define OB_USER_SRAM2_PE ((uint32_t)0x0400) /*!< SRAM2 parity check enable */ 282 #define OB_USER_SRAM2_RST ((uint32_t)0x0800) /*!< SRAM2 Erase when system reset */ 283 #define OB_USER_nRST_SHDW ((uint32_t)0x1000) /*!< Reset generated when entering the shutdown mode */ 284 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ 285 defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 286 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 287 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 288 #define OB_USER_nSWBOOT0 ((uint32_t)0x2000) /*!< Software BOOT0 */ 289 #define OB_USER_nBOOT0 ((uint32_t)0x4000) /*!< nBOOT0 option bit */ 290 #endif 291 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 292 #define OB_USER_DBANK ((uint32_t)0x8000) /*!< Single bank with 128-bits data or two banks with 64-bits data */ 293 #endif 294 /** 295 * @} 296 */ 297 298 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level 299 * @{ 300 */ 301 #define OB_BOR_LEVEL_0 ((uint32_t)FLASH_OPTR_BOR_LEV_0) /*!< Reset level threshold is around 1.7V */ 302 #define OB_BOR_LEVEL_1 ((uint32_t)FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.0V */ 303 #define OB_BOR_LEVEL_2 ((uint32_t)FLASH_OPTR_BOR_LEV_2) /*!< Reset level threshold is around 2.2V */ 304 #define OB_BOR_LEVEL_3 ((uint32_t)FLASH_OPTR_BOR_LEV_3) /*!< Reset level threshold is around 2.5V */ 305 #define OB_BOR_LEVEL_4 ((uint32_t)FLASH_OPTR_BOR_LEV_4) /*!< Reset level threshold is around 2.8V */ 306 /** 307 * @} 308 */ 309 310 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 311 * @{ 312 */ 313 #define OB_STOP_RST ((uint32_t)0x0000) /*!< Reset generated when entering the stop mode */ 314 #define OB_STOP_NORST ((uint32_t)FLASH_OPTR_nRST_STOP) /*!< No reset generated when entering the stop mode */ 315 /** 316 * @} 317 */ 318 319 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby 320 * @{ 321 */ 322 #define OB_STANDBY_RST ((uint32_t)0x0000) /*!< Reset generated when entering the standby mode */ 323 #define OB_STANDBY_NORST ((uint32_t)FLASH_OPTR_nRST_STDBY) /*!< No reset generated when entering the standby mode */ 324 /** 325 * @} 326 */ 327 328 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown 329 * @{ 330 */ 331 #define OB_SHUTDOWN_RST ((uint32_t)0x0000) /*!< Reset generated when entering the shutdown mode */ 332 #define OB_SHUTDOWN_NORST ((uint32_t)FLASH_OPTR_nRST_SHDW) /*!< No reset generated when entering the shutdown mode */ 333 /** 334 * @} 335 */ 336 337 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 338 * @{ 339 */ 340 #define OB_IWDG_HW ((uint32_t)0x00000) /*!< Hardware independent watchdog */ 341 #define OB_IWDG_SW ((uint32_t)FLASH_OPTR_IWDG_SW) /*!< Software independent watchdog */ 342 /** 343 * @} 344 */ 345 346 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop 347 * @{ 348 */ 349 #define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Stop mode */ 350 #define OB_IWDG_STOP_RUN ((uint32_t)FLASH_OPTR_IWDG_STOP) /*!< Independent watchdog counter is running in Stop mode */ 351 /** 352 * @} 353 */ 354 355 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby 356 * @{ 357 */ 358 #define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000) /*!< Independent watchdog counter is frozen in Standby mode */ 359 #define OB_IWDG_STDBY_RUN ((uint32_t)FLASH_OPTR_IWDG_STDBY) /*!< Independent watchdog counter is running in Standby mode */ 360 /** 361 * @} 362 */ 363 364 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 365 * @{ 366 */ 367 #define OB_WWDG_HW ((uint32_t)0x00000) /*!< Hardware window watchdog */ 368 #define OB_WWDG_SW ((uint32_t)FLASH_OPTR_WWDG_SW) /*!< Software window watchdog */ 369 /** 370 * @} 371 */ 372 373 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 374 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 375 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 376 /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode 377 * @{ 378 */ 379 #define OB_BFB2_DISABLE ((uint32_t)0x000000) /*!< Dual-bank boot disable */ 380 #define OB_BFB2_ENABLE ((uint32_t)FLASH_OPTR_BFB2) /*!< Dual-bank boot enable */ 381 /** 382 * @} 383 */ 384 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 385 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type 386 * @{ 387 */ 388 #define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 1 MB/512 kB Single-bank Flash */ 389 #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DB1M) /*!< 1 MB/512 kB Dual-bank Flash */ 390 /** 391 * @} 392 */ 393 #else 394 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type 395 * @{ 396 */ 397 #define OB_DUALBANK_SINGLE ((uint32_t)0x000000) /*!< 256 KB/512 KB Single-bank Flash */ 398 #define OB_DUALBANK_DUAL ((uint32_t)FLASH_OPTR_DUALBANK) /*!< 256 KB/512 KB Dual-bank Flash */ 399 /** 400 * @} 401 */ 402 #endif 403 #endif 404 405 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 406 /** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type 407 * @{ 408 */ 409 #define OB_DBANK_128_BITS ((uint32_t)0x000000) /*!< Single-bank with 128-bits data */ 410 #define OB_DBANK_64_BITS ((uint32_t)FLASH_OPTR_DBANK) /*!< Dual-bank with 64-bits data */ 411 #endif 412 /** 413 * @} 414 */ 415 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type 416 * @{ 417 */ 418 #define OB_BOOT1_SRAM ((uint32_t)0x000000) /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */ 419 #define OB_BOOT1_SYSTEM ((uint32_t)FLASH_OPTR_nBOOT1) /*!< System memory is selected as boot space (if BOOT0=1) */ 420 /** 421 * @} 422 */ 423 424 /** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type 425 * @{ 426 */ 427 #define OB_SRAM2_PARITY_ENABLE ((uint32_t)0x0000000) /*!< SRAM2 parity check enable */ 428 #define OB_SRAM2_PARITY_DISABLE ((uint32_t)FLASH_OPTR_SRAM2_PE) /*!< SRAM2 parity check disable */ 429 /** 430 * @} 431 */ 432 433 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type 434 * @{ 435 */ 436 #define OB_SRAM2_RST_ERASE ((uint32_t)0x0000000) /*!< SRAM2 erased when a system reset occurs */ 437 #define OB_SRAM2_RST_NOT_ERASE ((uint32_t)FLASH_OPTR_SRAM2_RST) /*!< SRAM2 is not erased when a system reset occurs */ 438 /** 439 * @} 440 */ 441 442 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ 443 defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 444 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 445 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 446 /** @defgroup OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 447 * @{ 448 */ 449 #define OB_BOOT0_FROM_OB ((uint32_t)0x0000000) /*!< BOOT0 taken from the option bit nBOOT0 */ 450 #define OB_BOOT0_FROM_PIN ((uint32_t)FLASH_OPTR_nSWBOOT0) /*!< BOOT0 taken from PH3/BOOT0 pin */ 451 /** 452 * @} 453 */ 454 455 /** @defgroup OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit 456 * @{ 457 */ 458 #define OB_BOOT0_RESET ((uint32_t)0x0000000) /*!< nBOOT0 = 0 */ 459 #define OB_BOOT0_SET ((uint32_t)FLASH_OPTR_nBOOT0) /*!< nBOOT0 = 1 */ 460 /** 461 * @} 462 */ 463 #endif 464 465 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type 466 * @{ 467 */ 468 #define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000) /*!< PCROP area is not erased when the RDP level 469 is decreased from Level 1 to Level 0 */ 470 #define OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is 471 decreased from Level 1 to Level 0 (full mass erase) */ 472 /** 473 * @} 474 */ 475 476 /** @defgroup FLASH_Latency FLASH Latency 477 * @{ 478 */ 479 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 480 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 481 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 482 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 483 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ 484 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 485 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */ 486 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */ 487 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ 488 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ 489 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */ 490 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */ 491 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */ 492 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */ 493 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */ 494 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */ 495 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */ 496 #endif 497 /** 498 * @} 499 */ 500 501 /** @defgroup FLASH_Keys FLASH Keys 502 * @{ 503 */ 504 #define FLASH_KEY1 0x45670123U /*!< Flash key1 */ 505 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 506 to unlock the FLASH registers access */ 507 508 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ 509 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 510 to unlock the RUN_PD bit in FLASH_ACR */ 511 512 #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ 513 #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 514 to allow option bytes operations */ 515 /** 516 * @} 517 */ 518 519 /** @defgroup FLASH_Flags FLASH Flags Definition 520 * @{ 521 */ 522 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */ 523 #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */ 524 #define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */ 525 #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */ 526 #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */ 527 #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ 528 #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */ 529 #define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */ 530 #define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */ 531 #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */ 532 #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */ 533 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ 534 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ 535 defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ 536 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 537 #define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /*!< FLASH Program empty */ 538 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 539 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 540 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 541 FLASH_FLAG_OPTVERR | FLASH_FLAG_PEMPTY) 542 #else 543 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 544 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 545 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 546 FLASH_FLAG_OPTVERR) 547 #endif 548 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ 549 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ 550 551 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 552 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 553 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ 554 FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCD) 555 /** 556 * @} 557 */ 558 559 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition 560 * @brief FLASH Interrupt definition 561 * @{ 562 */ 563 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ 564 #define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */ 565 #define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source*/ 566 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ 567 /** 568 * @} 569 */ 570 571 /* Exported macros -----------------------------------------------------------*/ 572 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros 573 * @brief macros to control FLASH features 574 * @{ 575 */ 576 577 /** 578 * @brief Set the FLASH Latency. 579 * @param __LATENCY__: FLASH Latency 580 * This parameter can be one of the following values : 581 * @arg FLASH_LATENCY_0: FLASH Zero wait state 582 * @arg FLASH_LATENCY_1: FLASH One wait state 583 * @arg FLASH_LATENCY_2: FLASH Two wait states 584 * @arg FLASH_LATENCY_3: FLASH Three wait states 585 * @arg FLASH_LATENCY_4: FLASH Four wait states 586 * @retval None 587 */ 588 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))) 589 590 /** 591 * @brief Get the FLASH Latency. 592 * @retval FLASH Latency 593 * This parameter can be one of the following values : 594 * @arg FLASH_LATENCY_0: FLASH Zero wait state 595 * @arg FLASH_LATENCY_1: FLASH One wait state 596 * @arg FLASH_LATENCY_2: FLASH Two wait states 597 * @arg FLASH_LATENCY_3: FLASH Three wait states 598 * @arg FLASH_LATENCY_4: FLASH Four wait states 599 */ 600 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) 601 602 /** 603 * @brief Enable the FLASH prefetch buffer. 604 * @retval None 605 */ 606 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 607 608 /** 609 * @brief Disable the FLASH prefetch buffer. 610 * @retval None 611 */ 612 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) 613 614 /** 615 * @brief Enable the FLASH instruction cache. 616 * @retval none 617 */ 618 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) 619 620 /** 621 * @brief Disable the FLASH instruction cache. 622 * @retval none 623 */ 624 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) 625 626 /** 627 * @brief Enable the FLASH data cache. 628 * @retval none 629 */ 630 #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) 631 632 /** 633 * @brief Disable the FLASH data cache. 634 * @retval none 635 */ 636 #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) 637 638 /** 639 * @brief Reset the FLASH instruction Cache. 640 * @note This function must be used only when the Instruction Cache is disabled. 641 * @retval None 642 */ 643 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 644 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ 645 } while (0) 646 647 /** 648 * @brief Reset the FLASH data Cache. 649 * @note This function must be used only when the data Cache is disabled. 650 * @retval None 651 */ 652 #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 653 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ 654 } while (0) 655 656 /** 657 * @brief Enable the FLASH power down during Low-power run mode. 658 * @note Writing this bit to 0 this bit, automatically the keys are 659 * loss and a new unlock sequence is necessary to re-write it to 1. 660 */ 661 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 662 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 663 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 664 } while (0) 665 666 /** 667 * @brief Disable the FLASH power down during Low-power run mode. 668 * @note Writing this bit to 0 this bit, automatically the keys are 669 * loss and a new unlock sequence is necessary to re-write it to 1. 670 */ 671 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 672 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 673 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 674 } while (0) 675 676 /** 677 * @brief Enable the FLASH power down during Low-Power sleep mode 678 * @retval none 679 */ 680 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 681 682 /** 683 * @brief Disable the FLASH power down during Low-Power sleep mode 684 * @retval none 685 */ 686 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 687 688 /** 689 * @} 690 */ 691 692 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros 693 * @brief macros to handle FLASH interrupts 694 * @{ 695 */ 696 697 /** 698 * @brief Enable the specified FLASH interrupt. 699 * @param __INTERRUPT__: FLASH interrupt 700 * This parameter can be any combination of the following values: 701 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 702 * @arg FLASH_IT_OPERR: Error Interrupt 703 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt 704 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 705 * @retval none 706 */ 707 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 708 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 709 } while(0) 710 711 /** 712 * @brief Disable the specified FLASH interrupt. 713 * @param __INTERRUPT__: FLASH interrupt 714 * This parameter can be any combination of the following values: 715 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 716 * @arg FLASH_IT_OPERR: Error Interrupt 717 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt 718 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 719 * @retval none 720 */ 721 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 722 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 723 } while(0) 724 725 /** 726 * @brief Check whether the specified FLASH flag is set or not. 727 * @param __FLAG__: specifies the FLASH flag to check. 728 * This parameter can be one of the following values: 729 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 730 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 731 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 732 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 733 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 734 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 735 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 736 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag 737 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag 738 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag 739 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag 740 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 741 * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices) 742 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 743 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 744 * @retval The new state of FLASH_FLAG (SET or RESET). 745 */ 746 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ 747 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 748 (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) 749 750 /** 751 * @brief Clear the FLASH's pending flags. 752 * @param __FLAG__: specifies the FLASH flags to clear. 753 * This parameter can be any combination of the following values: 754 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 755 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 756 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 757 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 758 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 759 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 760 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 761 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag 762 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag 763 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag 764 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag 765 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 766 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 767 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags 768 * @retval None 769 */ 770 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ 771 if(((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ 772 } while(0) 773 /** 774 * @} 775 */ 776 777 /* Include FLASH HAL Extended module */ 778 #include "stm32l4xx_hal_flash_ex.h" 779 #include "stm32l4xx_hal_flash_ramfunc.h" 780 781 /* Exported functions --------------------------------------------------------*/ 782 /** @addtogroup FLASH_Exported_Functions 783 * @{ 784 */ 785 786 /* Program operation functions ***********************************************/ 787 /** @addtogroup FLASH_Exported_Functions_Group1 788 * @{ 789 */ 790 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 791 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 792 /* FLASH IRQ handler method */ 793 void HAL_FLASH_IRQHandler(void); 794 /* Callbacks in non blocking modes */ 795 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 796 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 797 /** 798 * @} 799 */ 800 801 /* Peripheral Control functions **********************************************/ 802 /** @addtogroup FLASH_Exported_Functions_Group2 803 * @{ 804 */ 805 HAL_StatusTypeDef HAL_FLASH_Unlock(void); 806 HAL_StatusTypeDef HAL_FLASH_Lock(void); 807 /* Option bytes control */ 808 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 809 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 810 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 811 /** 812 * @} 813 */ 814 815 /* Peripheral State functions ************************************************/ 816 /** @addtogroup FLASH_Exported_Functions_Group3 817 * @{ 818 */ 819 uint32_t HAL_FLASH_GetError(void); 820 /** 821 * @} 822 */ 823 824 /** 825 * @} 826 */ 827 828 /* Private constants --------------------------------------------------------*/ 829 /** @defgroup FLASH_Private_Constants FLASH Private Constants 830 * @{ 831 */ 832 #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) 833 834 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 835 #define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x800U << 10U) : \ 836 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)) 837 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 838 #define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x200U << 10U) : \ 839 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)) 840 #elif defined (STM32L412xx) || defined (STM32L422xx) 841 #define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80U << 10U) : \ 842 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)) 843 #else 844 #define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x400U << 10U) : \ 845 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)) 846 #endif 847 848 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 849 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 850 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 851 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1U) 852 #else 853 #define FLASH_BANK_SIZE (FLASH_SIZE) 854 #endif 855 856 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 857 #define FLASH_PAGE_SIZE ((uint32_t)0x1000) 858 #define FLASH_PAGE_SIZE_128_BITS ((uint32_t)0x2000) 859 #else 860 #define FLASH_PAGE_SIZE ((uint32_t)0x800) 861 #endif 862 863 #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ 864 /** 865 * @} 866 */ 867 868 /* Private macros ------------------------------------------------------------*/ 869 /** @defgroup FLASH_Private_Macros FLASH Private Macros 870 * @{ 871 */ 872 873 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 874 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 875 876 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 877 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 878 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 879 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ 880 ((BANK) == FLASH_BANK_2) || \ 881 ((BANK) == FLASH_BANK_BOTH)) 882 883 #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ 884 ((BANK) == FLASH_BANK_2)) 885 #else 886 #define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) 887 888 #define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) 889 #endif 890 891 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ 892 ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ 893 ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) 894 895 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 896 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((ADDRESS) <= (FLASH_BASE+0x1FFFFFU))) 897 #else 898 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? \ 899 ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? \ 900 ((ADDRESS) <= (FLASH_BASE+0x7FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? \ 901 ((ADDRESS) <= (FLASH_BASE+0x3FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? \ 902 ((ADDRESS) <= (FLASH_BASE+0x1FFFFU)) : ((ADDRESS) <= (FLASH_BASE+0xFFFFFU))))))) 903 #endif 904 905 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU)) 906 907 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) 908 909 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 910 #define IS_FLASH_PAGE(PAGE) ((PAGE) < 256U) 911 #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 912 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? ((PAGE) < 256U) : \ 913 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 128U) : \ 914 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 64U) : \ 915 ((PAGE) < 256U))))) 916 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 917 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 256U) : \ 918 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \ 919 ((PAGE) < 256U)))) 920 #else 921 #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \ 922 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? ((PAGE) < 64U) : \ 923 ((PAGE) < 128U)))) 924 #endif 925 926 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP))) 927 928 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 929 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 930 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 931 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ 932 ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) 933 #else 934 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB)) 935 #endif 936 937 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ 938 ((LEVEL) == OB_RDP_LEVEL_1)/* ||\ 939 ((LEVEL) == OB_RDP_LEVEL_2)*/) 940 941 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 942 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFFU) && ((TYPE) != 0U)) 943 #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) 944 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFFU) && ((TYPE) != 0U)) 945 #else 946 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7FU) && ((TYPE) != 0U) && (((TYPE)&0x0180U) == 0U)) 947 #endif 948 949 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ 950 ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ 951 ((LEVEL) == OB_BOR_LEVEL_4)) 952 953 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) 954 955 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) 956 957 #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) 958 959 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) 960 961 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) 962 963 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) 964 965 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) 966 967 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 968 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 969 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 970 #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE)) 971 972 #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) 973 #endif 974 975 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 976 #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) 977 #endif 978 979 #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) 980 981 #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) 982 983 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) 984 985 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \ 986 defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ 987 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 988 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 989 #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) 990 991 #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET)) 992 #endif 993 994 #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE)) 995 996 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 997 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ 998 ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ 999 ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ 1000 ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ 1001 ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ 1002 ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ 1003 ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ 1004 ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) 1005 #else 1006 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ 1007 ((LATENCY) == FLASH_LATENCY_1) || \ 1008 ((LATENCY) == FLASH_LATENCY_2) || \ 1009 ((LATENCY) == FLASH_LATENCY_3) || \ 1010 ((LATENCY) == FLASH_LATENCY_4)) 1011 #endif 1012 /** 1013 * @} 1014 */ 1015 1016 /** 1017 * @} 1018 */ 1019 1020 /** 1021 * @} 1022 */ 1023 1024 /** 1025 * @} 1026 */ 1027 1028 #ifdef __cplusplus 1029 } 1030 #endif 1031 1032 #endif /* __STM32L4xx_HAL_FLASH_H */ 1033 1034 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1035
