1 /** 2 * \file 3 * 4 * \brief Component description for AES 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_AES_COMPONENT_ 30 #define _SAML21_AES_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR AES */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_AES Advanced Encryption Standard */ 36 /*@{*/ 37 38 #define AES_U2238 39 #define REV_AES 0x200 40 41 /* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ 48 uint32_t CFBS:3; /*!< bit: 5.. 7 CFB Types */ 49 uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Keysize */ 50 uint32_t CIPHER:1; /*!< bit: 10 Cipher mode */ 51 uint32_t STARTMODE:1; /*!< bit: 11 Start mode */ 52 uint32_t LOD:1; /*!< bit: 12 LOD Enable */ 53 uint32_t KEYGEN:1; /*!< bit: 13 Last key generation */ 54 uint32_t XORKEY:1; /*!< bit: 14 Xor Key operation */ 55 uint32_t :1; /*!< bit: 15 Reserved */ 56 uint32_t CTYPE:4; /*!< bit: 16..19 Counter measure types */ 57 uint32_t :12; /*!< bit: 20..31 Reserved */ 58 } bit; /*!< Structure used for bit access */ 59 uint32_t reg; /*!< Type used for register access */ 60 } AES_CTRLA_Type; 61 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 #define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ 64 #define AES_CTRLA_RESETVALUE _U(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ 65 66 #define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ 67 #define AES_CTRLA_SWRST (_U(0x1) << AES_CTRLA_SWRST_Pos) 68 #define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ 69 #define AES_CTRLA_ENABLE (_U(0x1) << AES_CTRLA_ENABLE_Pos) 70 #define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ 71 #define AES_CTRLA_AESMODE_Msk (_U(0x7) << AES_CTRLA_AESMODE_Pos) 72 #define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) 73 #define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) CFB Types */ 74 #define AES_CTRLA_CFBS_Msk (_U(0x7) << AES_CTRLA_CFBS_Pos) 75 #define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) 76 #define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Keysize */ 77 #define AES_CTRLA_KEYSIZE_Msk (_U(0x3) << AES_CTRLA_KEYSIZE_Pos) 78 #define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) 79 #define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher mode */ 80 #define AES_CTRLA_CIPHER (_U(0x1) << AES_CTRLA_CIPHER_Pos) 81 #define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start mode */ 82 #define AES_CTRLA_STARTMODE (_U(0x1) << AES_CTRLA_STARTMODE_Pos) 83 #define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) LOD Enable */ 84 #define AES_CTRLA_LOD (_U(0x1) << AES_CTRLA_LOD_Pos) 85 #define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last key generation */ 86 #define AES_CTRLA_KEYGEN (_U(0x1) << AES_CTRLA_KEYGEN_Pos) 87 #define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) Xor Key operation */ 88 #define AES_CTRLA_XORKEY (_U(0x1) << AES_CTRLA_XORKEY_Pos) 89 #define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter measure types */ 90 #define AES_CTRLA_CTYPE_Msk (_U(0xF) << AES_CTRLA_CTYPE_Pos) 91 #define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) 92 #define AES_CTRLA_MASK _U(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ 93 94 /* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ 95 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 96 typedef union { 97 struct { 98 uint8_t START:1; /*!< bit: 0 Manual Start */ 99 uint8_t NEWMSG:1; /*!< bit: 1 New message */ 100 uint8_t EOM:1; /*!< bit: 2 End of message */ 101 uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ 102 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 103 } bit; /*!< Structure used for bit access */ 104 uint8_t reg; /*!< Type used for register access */ 105 } AES_CTRLB_Type; 106 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 107 108 #define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ 109 #define AES_CTRLB_RESETVALUE _U(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ 110 111 #define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Manual Start */ 112 #define AES_CTRLB_START (_U(0x1) << AES_CTRLB_START_Pos) 113 #define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ 114 #define AES_CTRLB_NEWMSG (_U(0x1) << AES_CTRLB_NEWMSG_Pos) 115 #define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ 116 #define AES_CTRLB_EOM (_U(0x1) << AES_CTRLB_EOM_Pos) 117 #define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ 118 #define AES_CTRLB_GFMUL (_U(0x1) << AES_CTRLB_GFMUL_Pos) 119 #define AES_CTRLB_MASK _U(0x0F) /**< \brief (AES_CTRLB) MASK Register */ 120 121 /* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ 122 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 123 typedef union { 124 struct { 125 uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ 126 uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ 127 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 128 } bit; /*!< Structure used for bit access */ 129 uint8_t reg; /*!< Type used for register access */ 130 } AES_INTENCLR_Type; 131 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 132 133 #define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ 134 #define AES_INTENCLR_RESETVALUE _U(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ 135 136 #define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete */ 137 #define AES_INTENCLR_ENCCMP (_U(0x1) << AES_INTENCLR_ENCCMP_Pos) 138 #define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete */ 139 #define AES_INTENCLR_GFMCMP (_U(0x1) << AES_INTENCLR_GFMCMP_Pos) 140 #define AES_INTENCLR_MASK _U(0x03) /**< \brief (AES_INTENCLR) MASK Register */ 141 142 /* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ 143 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 144 typedef union { 145 struct { 146 uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ 147 uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ 148 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 149 } bit; /*!< Structure used for bit access */ 150 uint8_t reg; /*!< Type used for register access */ 151 } AES_INTENSET_Type; 152 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 153 154 #define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ 155 #define AES_INTENSET_RESETVALUE _U(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ 156 157 #define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete */ 158 #define AES_INTENSET_ENCCMP (_U(0x1) << AES_INTENSET_ENCCMP_Pos) 159 #define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete */ 160 #define AES_INTENSET_GFMCMP (_U(0x1) << AES_INTENSET_GFMCMP_Pos) 161 #define AES_INTENSET_MASK _U(0x03) /**< \brief (AES_INTENSET) MASK Register */ 162 163 /* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ 164 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 165 typedef union { // __I to avoid read-modify-write on write-to-clear register 166 struct { 167 __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ 168 __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ 169 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ 170 } bit; /*!< Structure used for bit access */ 171 uint8_t reg; /*!< Type used for register access */ 172 } AES_INTFLAG_Type; 173 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 174 175 #define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ 176 #define AES_INTFLAG_RESETVALUE _U(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ 177 178 #define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ 179 #define AES_INTFLAG_ENCCMP (_U(0x1) << AES_INTFLAG_ENCCMP_Pos) 180 #define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ 181 #define AES_INTFLAG_GFMCMP (_U(0x1) << AES_INTFLAG_GFMCMP_Pos) 182 #define AES_INTFLAG_MASK _U(0x03) /**< \brief (AES_INTFLAG) MASK Register */ 183 184 /* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ 185 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 186 typedef union { 187 struct { 188 uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ 189 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 190 } bit; /*!< Structure used for bit access */ 191 uint8_t reg; /*!< Type used for register access */ 192 } AES_DATABUFPTR_Type; 193 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 194 195 #define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ 196 #define AES_DATABUFPTR_RESETVALUE _U(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ 197 198 #define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ 199 #define AES_DATABUFPTR_INDATAPTR_Msk (_U(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) 200 #define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) 201 #define AES_DATABUFPTR_MASK _U(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ 202 203 /* -------- AES_DBGCTRL : (AES Offset: 0x09) ( /W 8) Debug control -------- */ 204 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 205 typedef union { 206 struct { 207 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 208 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 209 } bit; /*!< Structure used for bit access */ 210 uint8_t reg; /*!< Type used for register access */ 211 } AES_DBGCTRL_Type; 212 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 213 214 #define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ 215 #define AES_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ 216 217 #define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ 218 #define AES_DBGCTRL_DBGRUN (_U(0x1) << AES_DBGCTRL_DBGRUN_Pos) 219 #define AES_DBGCTRL_MASK _U(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ 220 221 /* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ 222 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 223 typedef union { 224 uint32_t reg; /*!< Type used for register access */ 225 } AES_KEYWORD_Type; 226 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 227 228 #define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ 229 #define AES_KEYWORD_RESETVALUE _U(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ 230 #define AES_KEYWORD_MASK _U(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ 231 232 /* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ 233 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 234 typedef union { 235 uint32_t reg; /*!< Type used for register access */ 236 } AES_INDATA_Type; 237 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 238 239 #define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ 240 #define AES_INDATA_RESETVALUE _U(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ 241 #define AES_INDATA_MASK _U(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ 242 243 /* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ 244 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 245 typedef union { 246 uint32_t reg; /*!< Type used for register access */ 247 } AES_INTVECTV_Type; 248 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 249 250 #define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ 251 #define AES_INTVECTV_RESETVALUE _U(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ 252 #define AES_INTVECTV_MASK _U(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ 253 254 /* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ 255 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 256 typedef union { 257 uint32_t reg; /*!< Type used for register access */ 258 } AES_HASHKEY_Type; 259 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 260 261 #define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ 262 #define AES_HASHKEY_RESETVALUE _U(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ 263 #define AES_HASHKEY_MASK _U(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ 264 265 /* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ 266 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 267 typedef union { 268 uint32_t reg; /*!< Type used for register access */ 269 } AES_GHASH_Type; 270 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 271 272 #define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ 273 #define AES_GHASH_RESETVALUE _U(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ 274 #define AES_GHASH_MASK _U(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ 275 276 /* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ 277 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 278 typedef union { 279 uint32_t reg; /*!< Type used for register access */ 280 } AES_CIPLEN_Type; 281 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 282 283 #define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ 284 #define AES_CIPLEN_RESETVALUE _U(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ 285 #define AES_CIPLEN_MASK _U(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ 286 287 /* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ 288 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 289 typedef union { 290 uint32_t reg; /*!< Type used for register access */ 291 } AES_RANDSEED_Type; 292 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 293 294 #define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ 295 #define AES_RANDSEED_RESETVALUE _U(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ 296 #define AES_RANDSEED_MASK _U(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ 297 298 /** \brief AES hardware registers */ 299 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 300 typedef struct { 301 __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 302 __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ 303 __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ 304 __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ 305 __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ 306 __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ 307 __O AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 ( /W 8) Debug control */ 308 RoReg8 Reserved1[0x2]; 309 __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ 310 RoReg8 Reserved2[0xC]; 311 __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ 312 __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ 313 RoReg8 Reserved3[0x10]; 314 __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ 315 __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ 316 RoReg8 Reserved4[0x4]; 317 __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ 318 __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ 319 } Aes; 320 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 321 322 /*@}*/ 323 324 #endif /* _SAML21_AES_COMPONENT_ */ 325
