1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of STMicroelectronics nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 37 /* Define to prevent recursive inclusion -------------------------------------*/ 38 #ifndef __STM32L0xx_HAL_H 39 #define __STM32L0xx_HAL_H 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /* Includes ------------------------------------------------------------------*/ 46 #include "stm32l0xx_hal_conf.h" 47 48 /** @addtogroup STM32L0xx_HAL_Driver 49 * @{ 50 */ 51 52 /** @defgroup HAL HAL 53 * @{ 54 */ 55 /** @defgroup HAL_Exported_Constants HAL Exported Constants 56 * @{ 57 */ 58 59 /** @defgroup SYSCFG_BootMode Boot Mode 60 * @{ 61 */ 62 #define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000U) 63 #define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_CFGR1_BOOT_MODE_0) 64 #define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_CFGR1_BOOT_MODE) 65 66 /** 67 * @} 68 */ 69 70 /** @defgroup DBGMCU_Low_Power_Config DBGMCU Low Power Configuration 71 * @{ 72 */ 73 #define DBGMCU_SLEEP DBGMCU_CR_DBG_SLEEP 74 #define DBGMCU_STOP DBGMCU_CR_DBG_STOP 75 #define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY 76 #define IS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00U) && ((__PERIPH__) != 0x00U)) 77 78 79 /** 80 * @} 81 */ 82 83 #if defined (LCD_BASE) /* STM32L0x3xx only */ 84 /** @defgroup SYSCFG_LCD_EXT_CAPA SYSCFG LCD External Capacitors 85 * @{ 86 */ 87 #define SYSCFG_LCD_EXT_CAPA SYSCFG_CFGR2_CAPA /*!< Connection of internal Vlcd rail to external capacitors */ 88 #define SYSCFG_VLCD_PB2_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_0 /*!< Connection on PB2 */ 89 #define SYSCFG_VLCD_PB12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_1 /*!< Connection on PB12 */ 90 #define SYSCFG_VLCD_PB0_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_2 /*!< Connection on PB0 */ 91 #if defined (SYSCFG_CFGR2_CAPA_3) 92 #define SYSCFG_VLCD_PE11_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_3 /*!< Connection on PE11 */ 93 #endif 94 #if defined (SYSCFG_CFGR2_CAPA_4) 95 #define SYSCFG_VLCD_PE12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_4 /*!< Connection on PE12 */ 96 #endif 97 98 /** 99 * @} 100 */ 101 #endif 102 103 /** @defgroup SYSCFG_VREFINT_OUT_SELECT SYSCFG VREFINT Out Selection 104 * @{ 105 */ 106 #define SYSCFG_VREFINT_OUT_NONE ((uint32_t)0x00000000U) /* no pad connected */ 107 #define SYSCFG_VREFINT_OUT_PB0 SYSCFG_CFGR3_VREF_OUT_0 /* Selects PBO as output for the Vrefint */ 108 #define SYSCFG_VREFINT_OUT_PB1 SYSCFG_CFGR3_VREF_OUT_1 /* Selects PB1 as output for the Vrefint */ 109 #define SYSCFG_VREFINT_OUT_PB0_PB1 SYSCFG_CFGR3_VREF_OUT /* Selects PBO and PB1 as output for the Vrefint */ 110 111 #define IS_SYSCFG_VREFINT_OUT_SELECT(OUTPUT) (((OUTPUT) == SYSCFG_VREFINT_OUT_NONE) || \ 112 ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0) || \ 113 ((OUTPUT) == SYSCFG_VREFINT_OUT_PB1) || \ 114 ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0_PB1)) 115 /** 116 * @} 117 */ 118 119 /** @defgroup SYSCFG_flags_definition SYSCFG Flags Definition 120 * @{ 121 */ 122 #define SYSCFG_FLAG_VREFINT_READY SYSCFG_CFGR3_VREFINT_RDYF 123 124 #define IS_SYSCFG_FLAG(FLAG) ((FLAG) == SYSCFG_FLAG_VREFINT_READY)) 125 126 /** 127 * @} 128 */ 129 130 /** @defgroup SYSCFG_FastModePlus_GPIO Fast Mode Plus on GPIO 131 * @{ 132 */ 133 /** @brief Fast mode Plus driving capability on a specific GPIO 134 */ 135 #if defined (SYSCFG_CFGR2_I2C_PB6_FMP) 136 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /* Enable Fast Mode Plus on PB6 */ 137 #endif 138 #if defined (SYSCFG_CFGR2_I2C_PB7_FMP) 139 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP /* Enable Fast Mode Plus on PB7 */ 140 #endif 141 #if defined (SYSCFG_CFGR2_I2C_PB8_FMP) 142 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /* Enable Fast Mode Plus on PB8 */ 143 #endif 144 #if defined (SYSCFG_CFGR2_I2C_PB9_FMP) 145 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /* Enable Fast Mode Plus on PB9 */ 146 #endif 147 148 #define IS_SYSCFG_FASTMODEPLUS(PIN) ((((PIN) & (SYSCFG_FASTMODEPLUS_PB6)) == SYSCFG_FASTMODEPLUS_PB6) || \ 149 (((PIN) & (SYSCFG_FASTMODEPLUS_PB7)) == SYSCFG_FASTMODEPLUS_PB7) || \ 150 (((PIN) & (SYSCFG_FASTMODEPLUS_PB8)) == SYSCFG_FASTMODEPLUS_PB8) || \ 151 (((PIN) & (SYSCFG_FASTMODEPLUS_PB9)) == SYSCFG_FASTMODEPLUS_PB9) ) 152 /** 153 * @} 154 */ 155 /** 156 * @} 157 */ 158 159 /** @defgroup HAL_Exported_Macros HAL Exported Macros 160 * @{ 161 */ 162 163 /** @brief Freeze/Unfreeze Peripherals in Debug mode 164 */ 165 #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP) 166 /** 167 * @brief TIM2 Peripherals Debug mode 168 */ 169 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP) 170 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP) 171 #endif 172 173 #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP) 174 /** 175 * @brief TIM3 Peripherals Debug mode 176 */ 177 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP) 178 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP) 179 #endif 180 181 #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP) 182 /** 183 * @brief TIM6 Peripherals Debug mode 184 */ 185 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) 186 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) 187 #endif 188 189 #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP) 190 /** 191 * @brief TIM7 Peripherals Debug mode 192 */ 193 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) 194 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) 195 #endif 196 197 #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) 198 /** 199 * @brief RTC Peripherals Debug mode 200 */ 201 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) 202 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) 203 #endif 204 205 #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP) 206 /** 207 * @brief WWDG Peripherals Debug mode 208 */ 209 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) 210 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) 211 #endif 212 213 #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP) 214 /** 215 * @brief IWDG Peripherals Debug mode 216 */ 217 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) 218 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) 219 #endif 220 221 #if defined (DBGMCU_APB1_FZ_DBG_I2C1_STOP) 222 /** 223 * @brief I2C1 Peripherals Debug mode 224 */ 225 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP) 226 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP) 227 #endif 228 229 #if defined (DBGMCU_APB1_FZ_DBG_I2C2_STOP) 230 /** 231 * @brief I2C2 Peripherals Debug mode 232 */ 233 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP) 234 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP) 235 #endif 236 237 #if defined (DBGMCU_APB1_FZ_DBG_I2C3_STOP) 238 /** 239 * @brief I2C3 Peripherals Debug mode 240 */ 241 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP) 242 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP) 243 #endif 244 245 #if defined (DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) 246 /** 247 * @brief LPTIMER Peripherals Debug mode 248 */ 249 #define __HAL_DBGMCU_FREEZE_LPTIMER() SET_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) 250 #define __HAL_DBGMCU_UNFREEZE_LPTIMER() CLEAR_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) 251 #endif 252 253 #if defined (DBGMCU_APB2_FZ_DBG_TIM22_STOP) 254 /** 255 * @brief TIM22 Peripherals Debug mode 256 */ 257 #define __HAL_DBGMCU_FREEZE_TIM22() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP) 258 #define __HAL_DBGMCU_UNFREEZE_TIM22() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP) 259 #endif 260 261 #if defined (DBGMCU_APB2_FZ_DBG_TIM21_STOP) 262 /** 263 * @brief TIM21 Peripherals Debug mode 264 */ 265 #define __HAL_DBGMCU_FREEZE_TIM21() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP) 266 #define __HAL_DBGMCU_UNFREEZE_TIM21() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP) 267 #endif 268 269 /** @brief Main Flash memory mapped at 0x00000000 270 */ 271 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) 272 273 /** @brief System Flash memory mapped at 0x00000000 274 */ 275 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0) 276 277 278 /** @brief Embedded SRAM mapped at 0x00000000 279 */ 280 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1) 281 282 /** @brief Configuration of the DBG Low Power mode. 283 * @param __DBGLPMODE__: bit field to indicate in wich Low Power mode DBG is still active. 284 * This parameter can be a value of 285 * - DBGMCU_SLEEP 286 * - DBGMCU_STOP 287 * - DBGMCU_STANDBY 288 */ 289 #define __HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__) do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); \ 290 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); \ 291 } while (0) 292 293 #if defined (LCD_BASE) /* STM32L0x3xx only */ 294 295 /** @brief Macro to configure the VLCD Decoupling capacitance connection. 296 * 297 * @param __SYSCFG_VLCD_CAPA__: specifies the decoupling of LCD capacitance for rails connection on GPIO. 298 * This parameter can be a combination of following values (when available): 299 * @arg SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2 300 * @arg SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12 301 * @arg SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0 302 * @arg SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11 303 * @arg SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12 304 * @retval None 305 */ 306 #define __HAL_SYSCFG_VLCD_CAPA_CONFIG(__SYSCFG_VLCD_CAPA__) \ 307 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA, (uint32_t)(__SYSCFG_VLCD_CAPA__)) 308 309 /** 310 * @brief Returns the decoupling of LCD capacitance configured by user. 311 * @retval The LCD capacitance connection as configured by user. The returned can be a combination of : 312 * SYSCFG_VLCD_PB2_EXT_CAPA_ON: Connection on PB2 313 * SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12 314 * SYSCFG_VLCD_PB0_EXT_CAPA_ON: Connection on PB0 315 * SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11 316 * SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12 317 */ 318 #define __HAL_SYSCFG_GET_VLCD_CAPA_CONFIG() READ_BIT(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA) 319 320 #endif 321 322 /** 323 * @brief Returns the boot mode as configured by user. 324 * @retval The boot mode as configured by user. The returned can be a value of : 325 * - SYSCFG_BOOT_MAINFLASH 326 * - SYSCFG_BOOT_SYSTEMFLASH 327 * - SYSCFG_BOOT_SRAM 328 */ 329 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE) 330 331 332 /** @brief Check whether the specified SYSCFG flag is set or not. 333 * @param __FLAG__: specifies the flag to check. 334 * The only parameter supported is SYSCFG_FLAG_VREFINT_READY 335 * @retval The new state of __FLAG__ (TRUE or FALSE). 336 */ 337 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) (((SYSCFG->CFGR3) & (__FLAG__)) == (__FLAG__)) 338 339 /** @brief Fast mode Plus driving capability enable macro 340 * @param __FASTMODEPLUS__: This parameter can be a value of : 341 * @arg SYSCFG_FASTMODEPLUS_PB6 342 * @arg SYSCFG_FASTMODEPLUS_PB7 343 * @arg SYSCFG_FASTMODEPLUS_PB8 344 * @arg SYSCFG_FASTMODEPLUS_PB9 345 */ 346 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ 347 SET_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \ 348 }while(0) 349 /** @brief Fast mode Plus driving capability disable macro 350 * @param __FASTMODEPLUS__: This parameter can be a value of : 351 * @arg SYSCFG_FASTMODEPLUS_PB6 352 * @arg SYSCFG_FASTMODEPLUS_PB7 353 * @arg SYSCFG_FASTMODEPLUS_PB8 354 * @arg SYSCFG_FASTMODEPLUS_PB9 355 */ 356 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ 357 CLEAR_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \ 358 }while(0) 359 360 361 /** 362 * @} 363 */ 364 365 /** @defgroup HAL_Exported_Functions HAL Exported Functions 366 * @{ 367 */ 368 /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization functions 369 * @brief Initialization and de-initialization functions 370 * @{ 371 */ 372 HAL_StatusTypeDef HAL_Init(void); 373 HAL_StatusTypeDef HAL_DeInit(void); 374 void HAL_MspInit(void); 375 void HAL_MspDeInit(void); 376 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); 377 378 /** 379 * @} 380 */ 381 382 /** @defgroup HAL_Exported_Functions_Group2 Peripheral Control functions 383 * @brief Peripheral Control functions 384 * @{ 385 */ 386 void HAL_IncTick(void); 387 void HAL_Delay(__IO uint32_t Delay); 388 uint32_t HAL_GetTick(void); 389 void HAL_SuspendTick(void); 390 void HAL_ResumeTick(void); 391 uint32_t HAL_GetHalVersion(void); 392 uint32_t HAL_GetREVID(void); 393 uint32_t HAL_GetDEVID(void); 394 void HAL_DBGMCU_EnableDBGSleepMode(void); 395 void HAL_DBGMCU_DisableDBGSleepMode(void); 396 void HAL_DBGMCU_EnableDBGStopMode(void); 397 void HAL_DBGMCU_DisableDBGStopMode(void); 398 void HAL_DBGMCU_EnableDBGStandbyMode(void); 399 void HAL_DBGMCU_DisableDBGStandbyMode(void); 400 void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph); 401 void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph); 402 uint32_t HAL_SYSCFG_GetBootMode(void); 403 void HAL_SYSCFG_Enable_Lock_VREFINT(void); 404 void HAL_SYSCFG_Disable_Lock_VREFINT(void); 405 void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT); 406 407 /** 408 * @} 409 */ 410 /** 411 * @} 412 */ 413 414 /* Define the private group ***********************************/ 415 /**************************************************************/ 416 /** @defgroup HAL_Private HAL Private 417 * @{ 418 */ 419 /** 420 * @} 421 */ 422 /**************************************************************/ 423 424 425 /** 426 * @} 427 */ 428 429 /** 430 * @} 431 */ 432 433 #ifdef __cplusplus 434 } 435 #endif 436 437 #endif /* __STM32L0xx_HAL_H */ 438 439 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 440 441
