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Searched refs:CFGR (Results 1 – 25 of 46) sorted by relevance

12

/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_ll_lptim.h393 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode); in LL_LPTIM_SetUpdateMode()
406 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); in LL_LPTIM_GetUpdateMode()
492 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode); in LL_LPTIM_SetCounterMode()
505 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); in LL_LPTIM_GetCounterMode()
527 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity); in LL_LPTIM_ConfigOutput()
541 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform); in LL_LPTIM_SetWaveform()
554 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE)); in LL_LPTIM_GetWaveform()
568 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity); in LL_LPTIM_SetPolarity()
581 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL)); in LL_LPTIM_GetPolarity()
606 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler); in LL_LPTIM_SetPrescaler()
[all …]
Dstm32l0xx_ll_crs.h340 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); in LL_CRS_SetReloadCounter()
350 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); in LL_CRS_GetReloadCounter()
362 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM); in LL_CRS_SetFreqErrorLimit()
372 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM); in LL_CRS_GetFreqErrorLimit()
391 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); in LL_CRS_SetSyncDivider()
409 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); in LL_CRS_GetSyncDivider()
423 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); in LL_CRS_SetSyncSignalSource()
436 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); in LL_CRS_GetSyncSignalSource()
449 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); in LL_CRS_SetSyncPolarity()
461 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); in LL_CRS_GetSyncPolarity()
[all …]
Dstm32l0xx_ll_rcc.h1307 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); in LL_RCC_SetSysClkSource()
1321 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); in LL_RCC_GetSysClkSource()
1341 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); in LL_RCC_SetAHBPrescaler()
1357 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); in LL_RCC_SetAPB1Prescaler()
1373 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); in LL_RCC_SetAPB2Prescaler()
1392 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); in LL_RCC_GetAHBPrescaler()
1407 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); in LL_RCC_GetAPB1Prescaler()
1422 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); in LL_RCC_GetAPB2Prescaler()
1435 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); in LL_RCC_SetClkAfterWakeFromStop()
1447 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK)); in LL_RCC_GetClkAfterWakeFromStop()
[all …]
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_lptim.h473 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode); in LL_LPTIM_SetUpdateMode()
486 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); in LL_LPTIM_GetUpdateMode()
598 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode); in LL_LPTIM_SetCounterMode()
611 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); in LL_LPTIM_GetCounterMode()
633 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity); in LL_LPTIM_ConfigOutput()
647 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform); in LL_LPTIM_SetWaveform()
660 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE)); in LL_LPTIM_GetWaveform()
674 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity); in LL_LPTIM_SetPolarity()
687 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL)); in LL_LPTIM_GetPolarity()
712 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler); in LL_LPTIM_SetPrescaler()
[all …]
Dstm32l4xx_ll_crs.h330 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); in LL_CRS_SetReloadCounter()
340 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); in LL_CRS_GetReloadCounter()
352 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); in LL_CRS_SetFreqErrorLimit()
362 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); in LL_CRS_GetFreqErrorLimit()
381 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); in LL_CRS_SetSyncDivider()
399 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); in LL_CRS_GetSyncDivider()
413 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); in LL_CRS_SetSyncSignalSource()
426 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); in LL_CRS_GetSyncSignalSource()
439 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); in LL_CRS_SetSyncPolarity()
451 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); in LL_CRS_GetSyncPolarity()
[all …]
Dstm32l4xx_ll_adc.h2636 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution); in LL_ADC_SetResolution()
2653 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)); in LL_ADC_GetResolution()
2673 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment); in LL_ADC_SetDataAlignment()
2688 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN)); in LL_ADC_GetDataAlignment()
2741 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode); in LL_ADC_SetLowPowerMode()
2789 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY)); in LL_ADC_GetLowPowerMode()
3127 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource); in LL_ADC_REG_SetTriggerSource()
3166 register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); in LL_ADC_REG_GetTriggerSource()
3193 …return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1U… in LL_ADC_REG_IsTriggerSourceSWStart()
3213 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge); in LL_ADC_REG_SetTriggerEdge()
[all …]
/loramac-node-2.7.6/src/boards/NucleoL073/cmsis/
Dsystem_stm32l0xx.c157 RCC->CFGR &= (uint32_t) 0x88FF400CU; in SystemInit()
169 RCC->CFGR &= (uint32_t)0xFF02FFFFU; in SystemInit()
225 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
241 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
242 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
246 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; in SystemCoreClockUpdate()
266 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; in SystemCoreClockUpdate()
/loramac-node-2.7.6/src/boards/B-L072Z-LRWAN1/cmsis/
Dsystem_stm32l0xx.c157 RCC->CFGR &= (uint32_t) 0x88FF400CU; in SystemInit()
169 RCC->CFGR &= (uint32_t)0xFF02FFFFU; in SystemInit()
225 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
241 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
242 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
246 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; in SystemCoreClockUpdate()
266 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; in SystemCoreClockUpdate()
/loramac-node-2.7.6/src/boards/SKiM881AXL/cmsis/
Dsystem_stm32l0xx.c157 RCC->CFGR &= (uint32_t) 0x88FF400CU; in SystemInit()
169 RCC->CFGR &= (uint32_t)0xFF02FFFFU; in SystemInit()
225 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
241 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
242 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
246 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; in SystemCoreClockUpdate()
266 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; in SystemCoreClockUpdate()
/loramac-node-2.7.6/src/boards/NucleoL152/cmsis/
Dsystem_stm32l1xx.c164 RCC->CFGR &= (uint32_t)0x88FFC00C; in SystemInit()
173 RCC->CFGR &= (uint32_t)0xFF02FFFF; in SystemInit()
232 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
248 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
249 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
253 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; in SystemCoreClockUpdate()
273 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; in SystemCoreClockUpdate()
/loramac-node-2.7.6/src/boards/SKiM980A/cmsis/
Dsystem_stm32l1xx.c164 RCC->CFGR &= (uint32_t)0x88FFC00C; in SystemInit()
173 RCC->CFGR &= (uint32_t)0xFF02FFFF; in SystemInit()
232 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
248 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
249 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
253 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; in SystemCoreClockUpdate()
273 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; in SystemCoreClockUpdate()
/loramac-node-2.7.6/src/boards/NAMote72/cmsis/
Dsystem_stm32l1xx.c164 RCC->CFGR &= (uint32_t)0x88FFC00C; in SystemInit()
173 RCC->CFGR &= (uint32_t)0xFF02FFFF; in SystemInit()
232 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
248 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
249 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
253 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; in SystemCoreClockUpdate()
273 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; in SystemCoreClockUpdate()
/loramac-node-2.7.6/src/boards/SKiM880B/cmsis/
Dsystem_stm32l1xx.c164 RCC->CFGR &= (uint32_t)0x88FFC00C; in SystemInit()
173 RCC->CFGR &= (uint32_t)0xFF02FFFF; in SystemInit()
232 tmp = RCC->CFGR & RCC_CFGR_SWS; in SystemCoreClockUpdate()
248 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
249 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
253 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; in SystemCoreClockUpdate()
273 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; in SystemCoreClockUpdate()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_hal_rcc.c265 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); in HAL_RCC_DeInit()
270 CLEAR_REG(RCC->CFGR); in HAL_RCC_DeInit()
474 … >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_BITNUMBER)]; in HAL_RCC_OscConfig()
778 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); in HAL_RCC_ClockConfig()
886 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); in HAL_RCC_ClockConfig()
893 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); in HAL_RCC_ClockConfig()
897 …SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFG… in HAL_RCC_ClockConfig()
1032 tmpreg = RCC->CFGR; in HAL_RCC_GetSysClockFreq()
1098 …return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITN… in HAL_RCC_GetPCLK1Freq()
1110 …return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNU… in HAL_RCC_GetPCLK2Freq()
[all …]
Dstm32l1xx_ll_rcc.c116 LL_RCC_WriteReg(CFGR, vl_mask); in LL_RCC_DeInit()
127 LL_RCC_WriteReg(CFGR, 0x00000000U); in LL_RCC_DeInit()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
Dstm32l0xx_hal_lptim.c207 tmpcfgr = hlptim->Instance->CFGR; in HAL_LPTIM_Init()
244 hlptim->Instance->CFGR = tmpcfgr; in HAL_LPTIM_Init()
365 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; in HAL_LPTIM_PWM_Start()
429 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; in HAL_LPTIM_PWM_Start_IT()
531 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; in HAL_LPTIM_OnePulse_Start()
595 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; in HAL_LPTIM_OnePulse_Start_IT()
697 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; in HAL_LPTIM_SetOnce_Start()
761 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; in HAL_LPTIM_SetOnce_Start_IT()
866 tmpcfgr = hlptim->Instance->CFGR; in HAL_LPTIM_Encoder_Start()
875 hlptim->Instance->CFGR = tmpcfgr; in HAL_LPTIM_Encoder_Start()
[all …]
Dstm32l0xx_hal_rcc.c279 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); in HAL_RCC_DeInit()
301 CLEAR_REG(RCC->CFGR); in HAL_RCC_DeInit()
505 … >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_BITNUMBER)]; in HAL_RCC_OscConfig()
854 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); in HAL_RCC_ClockConfig()
962 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); in HAL_RCC_ClockConfig()
969 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); in HAL_RCC_ClockConfig()
973 …SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFG… in HAL_RCC_ClockConfig()
1159 tmpreg = RCC->CFGR; in HAL_RCC_GetSysClockFreq()
1238 …return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITN… in HAL_RCC_GetPCLK1Freq()
1250 …return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNU… in HAL_RCC_GetPCLK2Freq()
[all …]
Dstm32l0xx_hal_rcc_ex.c475 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in HAL_RCCEx_GetPeriphCLKFreq()
476 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in HAL_RCCEx_GetPeriphCLKFreq()
888 WRITE_REG(CRS->CFGR, value); in HAL_RCCEx_CRSConfig()
920 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); in HAL_RCCEx_CRSGetSynchronizationInfo()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_lptim.c282 tmpcfgr = hlptim->Instance->CFGR; in HAL_LPTIM_Init()
319 hlptim->Instance->CFGR = tmpcfgr; in HAL_LPTIM_Init()
469 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; in HAL_LPTIM_PWM_Start()
541 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; in HAL_LPTIM_PWM_Start_IT()
667 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; in HAL_LPTIM_OnePulse_Start()
739 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; in HAL_LPTIM_OnePulse_Start_IT()
865 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; in HAL_LPTIM_SetOnce_Start()
937 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; in HAL_LPTIM_SetOnce_Start_IT()
1069 tmpcfgr = hlptim->Instance->CFGR; in HAL_LPTIM_Encoder_Start()
1078 hlptim->Instance->CFGR = tmpcfgr; in HAL_LPTIM_Encoder_Start()
[all …]
Dstm32l4xx_hal_rcc.c304 CLEAR_REG(RCC->CFGR); in HAL_RCC_DeInit()
320 while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) in HAL_RCC_DeInit()
486 …SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >… in HAL_RCC_OscConfig()
1098 if(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) in HAL_RCC_ClockConfig()
1101 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); in HAL_RCC_ClockConfig()
1107 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); in HAL_RCC_ClockConfig()
1151 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); in HAL_RCC_ClockConfig()
1158 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); in HAL_RCC_ClockConfig()
1176 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); in HAL_RCC_ClockConfig()
1184 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); in HAL_RCC_ClockConfig()
[all …]
Dstm32l4xx_hal_adc.c618 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); in HAL_ADC_Init()
636 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); in HAL_ADC_Init()
748 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM); in HAL_ADC_DeInit()
794 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS); in HAL_ADC_DeInit()
795 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); in HAL_ADC_DeInit()
1311 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) in HAL_ADC_Start()
1326 if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) in HAL_ADC_Start()
1333 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) in HAL_ADC_Start()
1454 if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) in HAL_ADC_PollForConversion()
1479 if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) in HAL_ADC_PollForConversion()
[all …]
Dstm32l4xx_hal_adc_ex.c324 tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); in HAL_ADCEx_InjectedStart()
564 tmp_cfgr = READ_REG(hadc->Instance->CFGR); in HAL_ADCEx_InjectedPollForConversion()
569 tmp_cfgr = READ_REG(tmpADC_Master->CFGR); in HAL_ADCEx_InjectedPollForConversion()
572 tmp_cfgr = READ_REG(hadc->Instance->CFGR); in HAL_ADCEx_InjectedPollForConversion()
665 tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); in HAL_ADCEx_InjectedStart_IT()
726 if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL) in HAL_ADCEx_InjectedStart_IT()
1412 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); in HAL_ADCEx_RegularStop_DMA()
1844 MODIFY_REG(hadc->Instance->CFGR, in HAL_ADCEx_InjectedConfigChannel()
1853 MODIFY_REG(hadc->Instance->CFGR, in HAL_ADCEx_InjectedConfigChannel()
1881 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); in HAL_ADCEx_InjectedConfigChannel()
[all …]
Dstm32l4xx_ll_adc.c598 MODIFY_REG(ADCx->CFGR, in LL_ADC_DeInit()
763 MODIFY_REG(ADCx->CFGR, in LL_ADC_Init()
863 MODIFY_REG(ADCx->CFGR, in LL_ADC_REG_Init()
882 MODIFY_REG(ADCx->CFGR, in LL_ADC_REG_Init()
992 MODIFY_REG(ADCx->CFGR, in LL_ADC_INJ_Init()
1002 MODIFY_REG(ADCx->CFGR, in LL_ADC_INJ_Init()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_rcc.h947 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); in LL_RCC_SetSysClkSource()
961 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); in LL_RCC_GetSysClkSource()
981 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); in LL_RCC_SetAHBPrescaler()
997 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); in LL_RCC_SetAPB1Prescaler()
1013 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); in LL_RCC_SetAPB2Prescaler()
1032 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); in LL_RCC_GetAHBPrescaler()
1047 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); in LL_RCC_GetAPB1Prescaler()
1062 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); in LL_RCC_GetAPB2Prescaler()
1096 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); in LL_RCC_ConfigMCO()
1256 …MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDi… in LL_RCC_PLL_ConfigDomain_SYS()
[all …]
/loramac-node-2.7.6/src/boards/NucleoL476/cmsis/
Dsystem_stm32l4xx.c208 RCC->CFGR = 0x00000000U; in SystemInit()
289 switch (RCC->CFGR & RCC_CFGR_SWS) in SystemCoreClockUpdate()
335 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; in SystemCoreClockUpdate()

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