Searched refs:BTCR (Results 1 – 9 of 9) sorted by relevance
| /loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/ |
| D | stm32l1xx_ll_fsmc.c | 206 … MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_ENABLE in FSMC_NORSRAM_Init()
224 …MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_DISABLE in FSMC_NORSRAM_Init()
266 Device->BTCR[Bank] = 0x000030DB; in FSMC_NORSRAM_DeInit()
271 Device->BTCR[Bank] = 0x000030D2; in FSMC_NORSRAM_DeInit()
274 Device->BTCR[Bank + 1] = 0x0FFFFFFF; in FSMC_NORSRAM_DeInit()
303 MODIFY_REG(Device->BTCR[Bank + 1], \ in FSMC_NORSRAM_Timing_Init()
396 SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); in FSMC_NORSRAM_WriteOperation_Enable()
414 CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); in FSMC_NORSRAM_WriteOperation_Disable()
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| /loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/ |
| D | stm32l4xx_ll_fmc.c | 290 MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (flashaccess | in FMC_NORSRAM_Init()
314 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
321 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
350 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
355 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
358 Device->BTCR[Bank + 1] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
392 …MODIFY_REG(Device->BTCR[Bank + 1], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
404 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
406 …tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos)… in FMC_NORSRAM_Timing_Init()
408 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
[all …]
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| /loramac-node-2.7.6/src/boards/NucleoL152/cmsis/ |
| D | system_stm32l1xx.c | 393 FSMC_Bank1->BTCR[4] = 0x00001011; in SystemInit_ExtMemCtl()
394 FSMC_Bank1->BTCR[5] = 0x00000300; in SystemInit_ExtMemCtl()
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| /loramac-node-2.7.6/src/boards/SKiM980A/cmsis/ |
| D | system_stm32l1xx.c | 393 FSMC_Bank1->BTCR[4] = 0x00001011; in SystemInit_ExtMemCtl()
394 FSMC_Bank1->BTCR[5] = 0x00000300; in SystemInit_ExtMemCtl()
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| /loramac-node-2.7.6/src/boards/NAMote72/cmsis/ |
| D | system_stm32l1xx.c | 393 FSMC_Bank1->BTCR[4] = 0x00001011; in SystemInit_ExtMemCtl()
394 FSMC_Bank1->BTCR[5] = 0x00000300; in SystemInit_ExtMemCtl()
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| /loramac-node-2.7.6/src/boards/SKiM880B/cmsis/ |
| D | system_stm32l1xx.c | 393 FSMC_Bank1->BTCR[4] = 0x00001011; in SystemInit_ExtMemCtl()
394 FSMC_Bank1->BTCR[5] = 0x00000300; in SystemInit_ExtMemCtl()
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| /loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/ |
| D | stm32l1xx_ll_fsmc.h | 497 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FS…
505 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], …
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| /loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/ |
| D | stm32l4xx_ll_fmc.h | 669 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx…
677 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR…
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| /loramac-node-2.7.6/src/boards/NucleoL476/cmsis/ |
| D | stm32l476xx.h | 518 …__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing… member
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