1 /* 2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE 3 * 4 * NOTE: This header file is not meant to be included directly. 5 */ 6 7 /* This header file contains assembly-language definitions (assembly 8 macros, etc.) for this specific Xtensa processor's TIE extensions 9 and options. It is customized to this Xtensa processor configuration. 10 11 Copyright (c) 1999-2022 Cadence Design Systems Inc. 12 13 Permission is hereby granted, free of charge, to any person obtaining 14 a copy of this software and associated documentation files (the 15 "Software"), to deal in the Software without restriction, including 16 without limitation the rights to use, copy, modify, merge, publish, 17 distribute, sublicense, and/or sell copies of the Software, and to 18 permit persons to whom the Software is furnished to do so, subject to 19 the following conditions: 20 21 The above copyright notice and this permission notice shall be included 22 in all copies or substantial portions of the Software. 23 24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 31 32 #ifndef _XTENSA_CORE_TIE_ASM_H 33 #define _XTENSA_CORE_TIE_ASM_H 34 35 #define XT_ADDI_A 1 36 #include <xtensa/coreasm.h> 37 38 /* Selection parameter values for save-area save/restore macros: */ 39 /* Option vs. TIE: */ 40 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 41 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 42 #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ 43 /* Whether used automatically by compiler: */ 44 #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 45 #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 46 #define XTHAL_SAS_ANYCC 0x000C /* both of the above */ 47 /* ABI handling across function calls: */ 48 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 49 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 50 #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 51 #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ 52 /* Misc */ 53 #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 54 #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ 55 | ((ccuse) & XTHAL_SAS_ANYCC) \ 56 | ((abi) & XTHAL_SAS_ANYABI) ) 57 58 59 /* 60 * Macro to store all non-coprocessor (extra) custom TIE and optional state 61 * (not including zero-overhead loop registers). 62 * Required parameters: 63 * ptr Save area pointer address register (clobbered) 64 * (register must contain a 4 byte aligned address). 65 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 66 * registers are clobbered, the remaining are unused). 67 * Optional parameters: 68 * continue If macro invoked as part of a larger store sequence, set to 1 69 * if this is not the first in the sequence. Defaults to 0. 70 * ofs Offset from start of larger sequence (from value of first ptr 71 * in sequence) at which to store. Defaults to next available space 72 * (or 0 if <continue> is 0). 73 * select Select what category(ies) of registers to store, as a bitmask 74 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 75 * alloc Select what category(ies) of registers to allocate; if any 76 * category is selected here that is not in <select>, space for 77 * the corresponding registers is skipped without doing any store. 78 */ 79 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 80 xchal_sa_start \continue, \ofs 81 // Optional global registers used by default by the compiler: 82 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 83 xchal_sa_align \ptr, 0, 1016, 4, 4 84 rur.threadptr \at1 // threadptr option 85 s32i \at1, \ptr, .Lxchal_ofs_+0 86 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 87 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 88 xchal_sa_align \ptr, 0, 1016, 4, 4 89 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 90 .endif 91 // Optional caller-saved registers used by default by the compiler: 92 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 93 xchal_sa_align \ptr, 0, 1012, 4, 4 94 rsr.acclo \at1 // MAC16 option 95 s32i \at1, \ptr, .Lxchal_ofs_+0 96 rsr.acchi \at1 // MAC16 option 97 s32i \at1, \ptr, .Lxchal_ofs_+4 98 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 99 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 100 xchal_sa_align \ptr, 0, 1012, 4, 4 101 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 102 .endif 103 // Optional caller-saved registers not used by default by the compiler: 104 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 105 xchal_sa_align \ptr, 0, 996, 4, 4 106 rsr.br \at1 // boolean option 107 s32i \at1, \ptr, .Lxchal_ofs_+0 108 rsr.scompare1 \at1 // conditional store option 109 s32i \at1, \ptr, .Lxchal_ofs_+4 110 rsr.m0 \at1 // MAC16 option 111 s32i \at1, \ptr, .Lxchal_ofs_+8 112 rsr.m1 \at1 // MAC16 option 113 s32i \at1, \ptr, .Lxchal_ofs_+12 114 rsr.m2 \at1 // MAC16 option 115 s32i \at1, \ptr, .Lxchal_ofs_+16 116 rsr.m3 \at1 // MAC16 option 117 s32i \at1, \ptr, .Lxchal_ofs_+20 118 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 119 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 120 xchal_sa_align \ptr, 0, 996, 4, 4 121 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 122 .endif 123 // Custom caller-saved registers not used by default by the compiler: 124 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 125 xchal_sa_align \ptr, 0, 1008, 4, 4 126 rur.f64r_lo \at1 // ureg 234 127 s32i \at1, \ptr, .Lxchal_ofs_+0 128 rur.f64r_hi \at1 // ureg 235 129 s32i \at1, \ptr, .Lxchal_ofs_+4 130 rur.f64s \at1 // ureg 236 131 s32i \at1, \ptr, .Lxchal_ofs_+8 132 .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 133 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 134 xchal_sa_align \ptr, 0, 1008, 4, 4 135 .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 136 .endif 137 .endm // xchal_ncp_store 138 139 /* 140 * Macro to load all non-coprocessor (extra) custom TIE and optional state 141 * (not including zero-overhead loop registers). 142 * Required parameters: 143 * ptr Save area pointer address register (clobbered) 144 * (register must contain a 4 byte aligned address). 145 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 146 * registers are clobbered, the remaining are unused). 147 * Optional parameters: 148 * continue If macro invoked as part of a larger load sequence, set to 1 149 * if this is not the first in the sequence. Defaults to 0. 150 * ofs Offset from start of larger sequence (from value of first ptr 151 * in sequence) at which to load. Defaults to next available space 152 * (or 0 if <continue> is 0). 153 * select Select what category(ies) of registers to load, as a bitmask 154 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 155 * alloc Select what category(ies) of registers to allocate; if any 156 * category is selected here that is not in <select>, space for 157 * the corresponding registers is skipped without doing any load. 158 */ 159 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 160 xchal_sa_start \continue, \ofs 161 // Optional global registers used by default by the compiler: 162 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 163 xchal_sa_align \ptr, 0, 1016, 4, 4 164 l32i \at1, \ptr, .Lxchal_ofs_+0 165 wur.threadptr \at1 // threadptr option 166 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 167 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 168 xchal_sa_align \ptr, 0, 1016, 4, 4 169 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 170 .endif 171 // Optional caller-saved registers used by default by the compiler: 172 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 173 xchal_sa_align \ptr, 0, 1012, 4, 4 174 l32i \at1, \ptr, .Lxchal_ofs_+0 175 wsr.acclo \at1 // MAC16 option 176 l32i \at1, \ptr, .Lxchal_ofs_+4 177 wsr.acchi \at1 // MAC16 option 178 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 179 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 180 xchal_sa_align \ptr, 0, 1012, 4, 4 181 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 182 .endif 183 // Optional caller-saved registers not used by default by the compiler: 184 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 185 xchal_sa_align \ptr, 0, 996, 4, 4 186 l32i \at1, \ptr, .Lxchal_ofs_+0 187 wsr.br \at1 // boolean option 188 l32i \at1, \ptr, .Lxchal_ofs_+4 189 wsr.scompare1 \at1 // conditional store option 190 l32i \at1, \ptr, .Lxchal_ofs_+8 191 wsr.m0 \at1 // MAC16 option 192 l32i \at1, \ptr, .Lxchal_ofs_+12 193 wsr.m1 \at1 // MAC16 option 194 l32i \at1, \ptr, .Lxchal_ofs_+16 195 wsr.m2 \at1 // MAC16 option 196 l32i \at1, \ptr, .Lxchal_ofs_+20 197 wsr.m3 \at1 // MAC16 option 198 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 199 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 200 xchal_sa_align \ptr, 0, 996, 4, 4 201 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 202 .endif 203 // Custom caller-saved registers not used by default by the compiler: 204 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 205 xchal_sa_align \ptr, 0, 1008, 4, 4 206 l32i \at1, \ptr, .Lxchal_ofs_+0 207 wur.f64r_lo \at1 // ureg 234 208 l32i \at1, \ptr, .Lxchal_ofs_+4 209 wur.f64r_hi \at1 // ureg 235 210 l32i \at1, \ptr, .Lxchal_ofs_+8 211 wur.f64s \at1 // ureg 236 212 .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 213 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 214 xchal_sa_align \ptr, 0, 1008, 4, 4 215 .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 216 .endif 217 .endm // xchal_ncp_load 218 219 220 #define XCHAL_NCP_NUM_ATMPS 1 221 222 /* 223 * Macro to store the state of TIE coprocessor AudioEngineLX. 224 * Required parameters: 225 * ptr Save area pointer address register (clobbered) 226 * (register must contain a 8 byte aligned address). 227 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS 228 * registers are clobbered, the remaining are unused). 229 * Optional parameters are the same as for xchal_ncp_store. 230 */ 231 #define xchal_cp_AudioEngineLX_store xchal_cp1_store 232 .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 233 xchal_sa_start \continue, \ofs 234 // Custom caller-saved registers not used by default by the compiler: 235 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 236 xchal_sa_align \ptr, 0, 0, 8, 8 237 ae_s64.i aed0, \ptr, .Lxchal_ofs_+40 238 ae_s64.i aed1, \ptr, .Lxchal_ofs_+48 239 ae_s64.i aed2, \ptr, .Lxchal_ofs_+56 240 addi \ptr, \ptr, 64 241 ae_s64.i aed3, \ptr, .Lxchal_ofs_+0 242 ae_s64.i aed4, \ptr, .Lxchal_ofs_+8 243 ae_s64.i aed5, \ptr, .Lxchal_ofs_+16 244 ae_s64.i aed6, \ptr, .Lxchal_ofs_+24 245 ae_s64.i aed7, \ptr, .Lxchal_ofs_+32 246 ae_s64.i aed8, \ptr, .Lxchal_ofs_+40 247 ae_s64.i aed9, \ptr, .Lxchal_ofs_+48 248 ae_s64.i aed10, \ptr, .Lxchal_ofs_+56 249 addi \ptr, \ptr, 64 250 ae_s64.i aed11, \ptr, .Lxchal_ofs_+0 251 ae_s64.i aed12, \ptr, .Lxchal_ofs_+8 252 ae_s64.i aed13, \ptr, .Lxchal_ofs_+16 253 ae_s64.i aed14, \ptr, .Lxchal_ofs_+24 254 ae_s64.i aed15, \ptr, .Lxchal_ofs_+32 255 ae_movae \at1, aep0 256 s8i \at1, \ptr, .Lxchal_ofs_+40 257 ae_movae \at1, aep1 258 s8i \at1, \ptr, .Lxchal_ofs_+41 259 ae_movae \at1, aep2 260 s8i \at1, \ptr, .Lxchal_ofs_+42 261 ae_movae \at1, aep3 262 s8i \at1, \ptr, .Lxchal_ofs_+43 263 ae_salign64.i u0, \ptr, .Lxchal_ofs_+48 264 ae_salign64.i u1, \ptr, .Lxchal_ofs_+56 265 addi \ptr, \ptr, 64 266 ae_salign64.i u2, \ptr, .Lxchal_ofs_+0 267 ae_salign64.i u3, \ptr, .Lxchal_ofs_+8 268 addi \ptr, \ptr, -192 269 ae_movvfcrfsr aed0 // ureg FCR_FSR 270 ae_s64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 271 rur.ae_ovf_sar \at1 // ureg 240 272 s32i \at1, \ptr, .Lxchal_ofs_+8 273 rur.ae_bithead \at1 // ureg 241 274 s32i \at1, \ptr, .Lxchal_ofs_+12 275 rur.ae_ts_fts_bu_bp \at1 // ureg 242 276 s32i \at1, \ptr, .Lxchal_ofs_+16 277 rur.ae_cw_sd_no \at1 // ureg 243 278 s32i \at1, \ptr, .Lxchal_ofs_+20 279 rur.ae_cbegin0 \at1 // ureg 246 280 s32i \at1, \ptr, .Lxchal_ofs_+24 281 rur.ae_cend0 \at1 // ureg 247 282 s32i \at1, \ptr, .Lxchal_ofs_+28 283 rur.ae_cbegin1 \at1 // ureg 248 284 s32i \at1, \ptr, .Lxchal_ofs_+32 285 rur.ae_cend1 \at1 // ureg 249 286 s32i \at1, \ptr, .Lxchal_ofs_+36 287 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 288 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 289 xchal_sa_align \ptr, 0, 0, 8, 8 290 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 291 .endif 292 .endm // xchal_cp1_store 293 294 /* 295 * Macro to load the state of TIE coprocessor AudioEngineLX. 296 * Required parameters: 297 * ptr Save area pointer address register (clobbered) 298 * (register must contain a 8 byte aligned address). 299 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS 300 * registers are clobbered, the remaining are unused). 301 * Optional parameters are the same as for xchal_ncp_load. 302 */ 303 #define xchal_cp_AudioEngineLX_load xchal_cp1_load 304 .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 305 xchal_sa_start \continue, \ofs 306 // Custom caller-saved registers not used by default by the compiler: 307 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 308 xchal_sa_align \ptr, 0, 0, 8, 8 309 ae_l64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 // ureg FCR_FSR 310 ae_movfcrfsrv aed0 311 l32i \at1, \ptr, .Lxchal_ofs_+8 312 wur.ae_ovf_sar \at1 // ureg 240 313 l32i \at1, \ptr, .Lxchal_ofs_+12 314 wur.ae_bithead \at1 // ureg 241 315 l32i \at1, \ptr, .Lxchal_ofs_+16 316 wur.ae_ts_fts_bu_bp \at1 // ureg 242 317 l32i \at1, \ptr, .Lxchal_ofs_+20 318 wur.ae_cw_sd_no \at1 // ureg 243 319 l32i \at1, \ptr, .Lxchal_ofs_+24 320 wur.ae_cbegin0 \at1 // ureg 246 321 l32i \at1, \ptr, .Lxchal_ofs_+28 322 wur.ae_cend0 \at1 // ureg 247 323 l32i \at1, \ptr, .Lxchal_ofs_+32 324 wur.ae_cbegin1 \at1 // ureg 248 325 l32i \at1, \ptr, .Lxchal_ofs_+36 326 wur.ae_cend1 \at1 // ureg 249 327 ae_l64.i aed0, \ptr, .Lxchal_ofs_+40 328 ae_l64.i aed1, \ptr, .Lxchal_ofs_+48 329 ae_l64.i aed2, \ptr, .Lxchal_ofs_+56 330 addi \ptr, \ptr, 64 331 ae_l64.i aed3, \ptr, .Lxchal_ofs_+0 332 ae_l64.i aed4, \ptr, .Lxchal_ofs_+8 333 ae_l64.i aed5, \ptr, .Lxchal_ofs_+16 334 ae_l64.i aed6, \ptr, .Lxchal_ofs_+24 335 ae_l64.i aed7, \ptr, .Lxchal_ofs_+32 336 ae_l64.i aed8, \ptr, .Lxchal_ofs_+40 337 ae_l64.i aed9, \ptr, .Lxchal_ofs_+48 338 ae_l64.i aed10, \ptr, .Lxchal_ofs_+56 339 addi \ptr, \ptr, 64 340 ae_l64.i aed11, \ptr, .Lxchal_ofs_+0 341 ae_l64.i aed12, \ptr, .Lxchal_ofs_+8 342 ae_l64.i aed13, \ptr, .Lxchal_ofs_+16 343 ae_l64.i aed14, \ptr, .Lxchal_ofs_+24 344 ae_l64.i aed15, \ptr, .Lxchal_ofs_+32 345 addi \ptr, \ptr, 40 346 l8ui \at1, \ptr, .Lxchal_ofs_+0 347 ae_movea aep0, \at1 348 l8ui \at1, \ptr, .Lxchal_ofs_+1 349 ae_movea aep1, \at1 350 l8ui \at1, \ptr, .Lxchal_ofs_+2 351 ae_movea aep2, \at1 352 l8ui \at1, \ptr, .Lxchal_ofs_+3 353 ae_movea aep3, \at1 354 addi \ptr, \ptr, 8 355 ae_lalign64.i u0, \ptr, .Lxchal_ofs_+0 356 ae_lalign64.i u1, \ptr, .Lxchal_ofs_+8 357 ae_lalign64.i u2, \ptr, .Lxchal_ofs_+16 358 ae_lalign64.i u3, \ptr, .Lxchal_ofs_+24 359 .set .Lxchal_pofs_, .Lxchal_pofs_ + 176 360 .set .Lxchal_ofs_, .Lxchal_ofs_ + 32 361 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 362 xchal_sa_align \ptr, 0, 0, 8, 8 363 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 364 .endif 365 .endm // xchal_cp1_load 366 367 #define XCHAL_CP1_NUM_ATMPS 1 368 #define XCHAL_SA_NUM_ATMPS 1 369 370 /* Empty macros for unconfigured coprocessors: */ 371 .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 372 .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 373 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 374 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 375 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 376 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 377 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 378 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 379 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 380 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 381 .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 382 .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 383 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 384 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 385 386 #endif /*_XTENSA_CORE_TIE_ASM_H*/ 387 388
