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Searched refs:XTHAL_SAM_WRITETHRU (Results 1 – 12 of 12) sorted by relevance

/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-matmap.h89 #define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \
90 XTHAL_SAM_WRITETHRU XCHAL_SEP \
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-matmap.h91 #define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \
92 XTHAL_SAM_WRITETHRU XCHAL_SEP \
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-matmap.h90 #define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \
91 XTHAL_SAM_WRITETHRU XCHAL_SEP \
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-matmap.h89 #define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \
90 XTHAL_SAM_WRITETHRU XCHAL_SEP \
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-matmap.h90 #define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \
91 XTHAL_SAM_WRITETHRU XCHAL_SEP \
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-matmap.h90 #define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \
91 XTHAL_SAM_WRITETHRU XCHAL_SEP \
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-matmap.h91 #define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \
92 XTHAL_SAM_WRITETHRU XCHAL_SEP \
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-matmap.h91 #define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \
92 XTHAL_SAM_WRITETHRU XCHAL_SEP \
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-matmap.h91 #define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \
92 XTHAL_SAM_WRITETHRU XCHAL_SEP \
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-matmap.h100 XTHAL_SAM_WRITETHRU XCHAL_SEP \
101 XTHAL_SAM_WRITETHRU XCHAL_SEP \
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-matmap.h99 XTHAL_SAM_WRITETHRU XCHAL_SEP \
100 XTHAL_SAM_WRITETHRU XCHAL_SEP \
/hal_xtensa-latest/include/xtensa/
Dhal.h595 #define XTHAL_SAM_WRITETHRU 0x02A /* -O-G-W-C- 2345789 writethrough */ macro