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Searched refs:XTHAL_MEMEP_ECC (Results 1 – 5 of 5) sorted by relevance

/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h297 #define XCHAL_ICACHE_ECC_PARITY XTHAL_MEMEP_ECC
298 #define XCHAL_DCACHE_ECC_PARITY XTHAL_MEMEP_ECC
324 #define XCHAL_INSTRAM0_ECC_PARITY XTHAL_MEMEP_ECC /* ECC/parity type, 0=none */
332 #define XCHAL_DATARAM0_ECC_PARITY XTHAL_MEMEP_ECC /* ECC/parity type, 0=none */
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h297 #define XCHAL_ICACHE_ECC_PARITY XTHAL_MEMEP_ECC
298 #define XCHAL_DCACHE_ECC_PARITY XTHAL_MEMEP_ECC
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h297 #define XCHAL_ICACHE_ECC_PARITY XTHAL_MEMEP_ECC
298 #define XCHAL_DCACHE_ECC_PARITY XTHAL_MEMEP_ECC
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h297 #define XCHAL_ICACHE_ECC_PARITY XTHAL_MEMEP_ECC
298 #define XCHAL_DCACHE_ECC_PARITY XTHAL_MEMEP_ECC
/hal_xtensa-latest/include/xtensa/
Dhal.h484 #define XTHAL_MEMEP_ECC 2 macro