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Searched refs:XTHAL_AR_RW (Results 1 – 4 of 4) sorted by relevance

/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-matmap.h71 #define XCHAL_CA_BYPASS_RW (XTHAL_AR_RW | XTHAL_MEM_DEVICE)
77 #define XCHAL_CA_RW (XTHAL_AR_RW)
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-matmap.h71 #define XCHAL_CA_BYPASS_RW (XTHAL_AR_RW | XTHAL_MEM_DEVICE)
77 #define XCHAL_CA_RW (XTHAL_AR_RW)
/hal_xtensa-latest/src/hal/
Dmpu.c220 case XTHAL_AR_RW: in is_kernel_readable()
240 case XTHAL_AR_RW: in is_kernel_writeable()
274 case XTHAL_AR_RW: in is_kernel_executable()
298 case XTHAL_AR_RW: in is_user_readable()
322 case XTHAL_AR_RW: in is_user_writeable()
341 case XTHAL_AR_RW: in is_user_executable()
/hal_xtensa-latest/include/xtensa/
Dhal.h1029 #define XTHAL_AR_RW 6 /* Kernel read/write, User no access */ macro