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Searched refs:XSHAL_TRAPNULL_CACHEATTR_WRITEBACK (Results 1 – 15 of 15) sorted by relevance

/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dsystem.h166 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2244442F /* enable caches in write-back mode */ macro
170 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
177 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
181 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dsystem.h166 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x22222244 /* enable caches in write-back mode */ macro
170 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
177 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
181 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dsystem.h166 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x22222211 /* enable caches in write-back mode */ macro
170 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
177 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
181 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dsystem.h183 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x22222244 /* enable caches in write-back mode */ macro
187 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
194 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
198 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dsystem.h172 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222111F /* enable caches in write-back mode */ macro
176 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
183 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
187 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dsystem.h183 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2224242F /* enable caches in write-back mode */ macro
187 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
194 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
198 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dsystem.h183 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222111F /* enable caches in write-back mode */ macro
187 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
194 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
198 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dsystem.h183 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222224F /* enable caches in write-back mode */ macro
187 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
194 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
198 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dsystem.h171 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x7733333C /* enable caches in write-back mode */ macro
175 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
182 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
186 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dsystem.h172 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x77333337 /* enable caches in write-back mode */ macro
176 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
183 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
187 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dsystem.h172 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x42422224 /* enable caches in write-back mode */ macro
176 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
183 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
187 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dsystem.h187 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2244222F /* enable caches in write-back mode */ macro
191 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
198 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
202 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dsystem.h187 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2244222F /* enable caches in write-back mode */ macro
191 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
198 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
202 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dsystem.h187 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2244222F /* enable caches in write-back mode */ macro
191 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
198 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
202 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dsystem.h187 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2244222F /* enable caches in write-back mode */ macro
191 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to e…
198 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
202 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK