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Searched refs:XCHAL_INTLEVEL7_ANDBELOW_MASK (Results 1 – 17 of 17) sorted by relevance

/hal_xtensa-latest/include/xtensa/config/
Dcore.h205 #define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
206 #define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
207 #define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
208 #define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
209 #define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
210 #define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
211 #define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
212 #define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
228 XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore.h242 #define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
243 #define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
244 #define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
245 #define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
246 #define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
247 #define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
248 #define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
249 #define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK
265 XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \
Dcore-isa.h452 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x007FFFFF macro
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h257 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h359 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x001FFFFF macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h359 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x001FFFFF macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h359 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x001FFFFF macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h382 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x001FFFFF macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h378 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h347 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h347 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h473 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x000001FF macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h473 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x000001FF macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h445 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x01FFFFFF macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h374 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h488 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h474 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF macro