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Searched refs:XCHAL_INTLEVEL6_VECTOR_VADDR (Results 1 – 7 of 7) sorted by relevance

/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h425 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280 macro
428 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h528 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0xBEFE0A80 macro
531 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h528 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0xBEFE0A80 macro
531 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h528 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0xBEFE0A80 macro
531 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h551 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x9F180A80 macro
554 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h564 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280 macro
567 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h660 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280 macro
663 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR