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Searched refs:XCHAL_INT20_EXTNUM (Results 1 – 11 of 11) sorted by relevance

/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h462 #define XCHAL_INT20_EXTNUM 7 /* (intlevel 7) */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h462 #define XCHAL_INT20_EXTNUM 7 /* (intlevel 7) */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h462 #define XCHAL_INT20_EXTNUM 7 /* (intlevel 7) */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h485 #define XCHAL_INT20_EXTNUM 7 /* (intlevel 7) */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h503 #define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h502 #define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h502 #define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h528 #define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h586 #define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h638 #define XCHAL_INT20_EXTNUM 16 /* (intlevel 2) */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h652 #define XCHAL_INT20_EXTNUM 16 /* (intlevel 2) */ macro