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Searched refs:XCHAL_HAVE_XEA5 (Results 1 – 4 of 4) sorted by relevance

/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h578 #define XCHAL_HAVE_XEA5 0 /* Exception Architecture 5 */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h576 #define XCHAL_HAVE_XEA5 0 /* Exception Architecture 5 */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h673 #define XCHAL_HAVE_XEA5 0 /* Exception Architecture 5 */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h687 #define XCHAL_HAVE_XEA5 0 /* Exception Architecture 5 (RNX) */ macro