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Searched refs:XCHAL_DATARAM0_BANKS (Results 1 – 10 of 10) sorted by relevance

/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h333 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h326 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h302 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h302 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h423 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h423 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h331 #define XCHAL_DATARAM0_BANKS 4 /* number of banks */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h398 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h423 #define XCHAL_DATARAM0_BANKS 4 /* number of banks */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h429 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ macro