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Searched refs:XCHAL_VECBASE_RESET_PADDR (Results 1 – 13 of 13) sorted by relevance

/hal_xtensa-3.7.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h386 #define XCHAL_VECBASE_RESET_PADDR 0x00002000 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h483 #define XCHAL_VECBASE_RESET_PADDR 0xBEFE0800 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h483 #define XCHAL_VECBASE_RESET_PADDR 0xBEFE0800 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h483 #define XCHAL_VECBASE_RESET_PADDR 0xBEFE0800 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h506 #define XCHAL_VECBASE_RESET_PADDR 0x9F180800 macro
/hal_xtensa-3.7.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h525 #define XCHAL_VECBASE_RESET_PADDR 0x40000000 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h588 #define XCHAL_VECBASE_RESET_PADDR 0x1FF80800 macro
/hal_xtensa-3.7.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h533 #define XCHAL_VECBASE_RESET_PADDR 0x3B6F8400 macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h533 #define XCHAL_VECBASE_RESET_PADDR 0x596F8400 macro
/hal_xtensa-3.7.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h618 #define XCHAL_VECBASE_RESET_PADDR 0x40000400 macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h560 #define XCHAL_VECBASE_RESET_PADDR 0x21170400 macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h683 #define XCHAL_VECBASE_RESET_PADDR 0x24020400 macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h698 #define XCHAL_VECBASE_RESET_PADDR 0x00000400 macro