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Searched refs:XCHAL_TRAX_TIME_WIDTH (Results 1 – 12 of 12) sorted by relevance

/hal_xtensa-3.7.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h562 #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h562 #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h562 #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h585 #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ macro
/hal_xtensa-3.7.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h598 #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h655 #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ macro
/hal_xtensa-3.7.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h600 #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h600 #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ macro
/hal_xtensa-3.7.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h679 #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h627 #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h750 #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h765 #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ macro