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Searched refs:XCHAL_NUM_DBREAK (Results 1 – 16 of 16) sorted by relevance

/hal_xtensa-3.7.0/src/hal/
Ddebug_hndlr.S103 #if XCHAL_NUM_DBREAK > 0
107 # if XCHAL_NUM_DBREAK > 1
Ddebug.c36 const int Xthal_num_dbreak = XCHAL_NUM_DBREAK;
/hal_xtensa-3.7.0/include/xtensa/
Dxtruntime-core-state.h110 # if XCHAL_NUM_DBREAK
111 STRUCT_AFIELD(long,4,CS_SA_,dbreakc, XCHAL_NUM_DBREAK)
112 STRUCT_AFIELD(long,4,CS_SA_,dbreaka, XCHAL_NUM_DBREAK)
/hal_xtensa-3.7.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h444 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h553 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h553 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h553 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h576 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/hal_xtensa-3.7.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h589 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h646 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/hal_xtensa-3.7.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h591 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h591 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/hal_xtensa-3.7.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h670 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h618 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h741 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h756 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro