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Searched refs:XCHAL_MPU_ALIGN_BITS (Results 1 – 11 of 11) sorted by relevance

/hal_xtensa-3.7.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h601 #define XCHAL_MPU_ALIGN_BITS 0 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h601 #define XCHAL_MPU_ALIGN_BITS 0 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h601 #define XCHAL_MPU_ALIGN_BITS 0 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h624 #define XCHAL_MPU_ALIGN_BITS 0 macro
/hal_xtensa-3.7.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h637 #define XCHAL_MPU_ALIGN_BITS 0 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h695 #define XCHAL_MPU_ALIGN_BITS 0 macro
/hal_xtensa-3.7.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h718 #define XCHAL_MPU_ALIGN_BITS 12 macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h666 #define XCHAL_MPU_ALIGN_BITS 0 macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h790 #define XCHAL_MPU_ALIGN_BITS 0 macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h805 #define XCHAL_MPU_ALIGN_BITS 0 macro
/hal_xtensa-3.7.0/src/hal/
Dmpu.c63 #define MPU_ADDRESS_MASK (0xffffffff << XCHAL_MPU_ALIGN_BITS)
66 #define MPU_VSTART_CORRECTNESS_MASK ((0x1 << (XCHAL_MPU_ALIGN_BITS)) - 1)