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Searched refs:XCHAL_HAVE_PIF_WR_RESP (Results 1 – 13 of 13) sorted by relevance

/hal_xtensa-3.7.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h281 #define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h281 #define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h281 #define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h281 #define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ macro
/hal_xtensa-3.7.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h274 #define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h359 #define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ macro
/hal_xtensa-3.7.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h251 #define XCHAL_HAVE_PIF_WR_RESP 1 /* pif write response */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h251 #define XCHAL_HAVE_PIF_WR_RESP 1 /* pif write response */ macro
/hal_xtensa-3.7.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h352 #define XCHAL_HAVE_PIF_WR_RESP 1 /* pif write response */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h279 #define XCHAL_HAVE_PIF_WR_RESP 1 /* pif write response */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h359 #define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h357 #define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ macro
/hal_xtensa-3.7.0/include/xtensa/config/
Dcore.h127 XCHAL_HAVE_PIF_WR_RESP && \