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Searched refs:XCHAL_HAVE_ICACHE_TEST (Results 1 – 14 of 14) sorted by relevance

/hal_xtensa-3.7.0/src/hal/
Dmem_ecc_parity.S189 # if XCHAL_ICACHE_SIZE && XCHAL_HAVE_ICACHE_TEST
Dcache_asm.S133 XCHAL_HAVE_ICACHE_TEST && XCHAL_HAVE_MINMAX && XCHAL_HAVE_LOOPS
/hal_xtensa-3.7.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h256 #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h256 #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h256 #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h256 #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ macro
/hal_xtensa-3.7.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h249 #define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h311 #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ macro
/hal_xtensa-3.7.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h229 #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h229 #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ macro
/hal_xtensa-3.7.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h304 #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h254 #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h311 #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h309 #define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ macro