Searched refs:XCHAL_HAVE_CACHEATTR (Results 1 – 16 of 16) sorted by relevance
38 #define XCHAL_CA_8X512 (XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEA…105 #if XCHAL_HAVE_CACHEATTR255 #if XCHAL_HAVE_CACHEATTR282 #if XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR400 #if XCHAL_HAVE_CACHEATTR
188 # if XCHAL_HAVE_CACHEATTR /* single CACHEATTR register used for both I and D */200 # if !XCHAL_HAVE_CACHEATTR /* possibly independent CACHEATTR states used for I and D */223 # if XCHAL_HAVE_CACHEATTR /* single CACHEATTR register used for both I and D accesses */235 #if XCHAL_HAVE_CACHEATTR292 #if XCHAL_HAVE_CACHEATTR
95 const unsigned char Xthal_have_cacheattr = XCHAL_HAVE_CACHEATTR;
458 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
578 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
601 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
614 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
671 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
616 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
694 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
643 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
766 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
781 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ macro
