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Searched refs:XCHAL_FUSIONG_SIMD32 (Results 1 – 10 of 10) sorted by relevance

/hal_xtensa-3.7.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h151 #define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h151 #define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h151 #define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h151 #define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ macro
/hal_xtensa-3.7.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h146 #define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ macro
/hal_xtensa-3.7.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h159 #define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ macro
/hal_xtensa-3.7.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h155 #define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h149 #define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h159 #define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h158 #define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ macro