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Searched refs:XCHAL_CP6_SA_SIZE (Results 1 – 15 of 15) sorted by relevance

/hal_xtensa-3.7.0/include/xtensa/
Dxtruntime-core-state.h195 #if XCHAL_CP6_SA_SIZE > 0
196 STRUCT_AFIELD_A(char,1,XCHAL_CP6_SA_ALIGN,CS_SA_,cp6,XCHAL_CP6_SA_SIZE)
/hal_xtensa-3.7.0/zephyr/soc/dc233c/xtensa/config/
Dtie.h60 #define XCHAL_CP6_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dtie.h60 #define XCHAL_CP6_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dtie.h60 #define XCHAL_CP6_SA_SIZE 0 macro
/hal_xtensa-3.7.0/src/hal/
Dstate.c46 XCHAL_CP6_SA_SIZE,
/hal_xtensa-3.7.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dtie.h60 #define XCHAL_CP6_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/mimx8ml8/xtensa/config/
Dtie.h58 #define XCHAL_CP6_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dtie.h60 #define XCHAL_CP6_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dtie.h58 #define XCHAL_CP6_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dtie.h60 #define XCHAL_CP6_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dtie.h58 #define XCHAL_CP6_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dtie.h63 #define XCHAL_CP6_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dtie.h63 #define XCHAL_CP6_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dtie.h63 #define XCHAL_CP6_SA_SIZE 0 macro
/hal_xtensa-3.7.0/include/xtensa/config/
Dcore.h1112 # if XCHAL_CP6_SA_SIZE == 0
1172 # if XCHAL_CP6_SA_SIZE
1233 # if XCHAL_CP6_SA_SIZE
1308 #define XCHAL_CP6_SA_SIZE 0 macro