Home
last modified time | relevance | path

Searched refs:XCHAL_CP5_SA_SIZE (Results 1 – 15 of 15) sorted by relevance

/hal_xtensa-3.7.0/include/xtensa/
Dxtruntime-core-state.h192 #if XCHAL_CP5_SA_SIZE > 0
193 STRUCT_AFIELD_A(char,1,XCHAL_CP5_SA_ALIGN,CS_SA_,cp5,XCHAL_CP5_SA_SIZE)
/hal_xtensa-3.7.0/zephyr/soc/dc233c/xtensa/config/
Dtie.h58 #define XCHAL_CP5_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dtie.h58 #define XCHAL_CP5_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dtie.h58 #define XCHAL_CP5_SA_SIZE 0 macro
/hal_xtensa-3.7.0/src/hal/
Dstate.c45 XCHAL_CP5_SA_SIZE,
/hal_xtensa-3.7.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dtie.h58 #define XCHAL_CP5_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/mimx8ml8/xtensa/config/
Dtie.h56 #define XCHAL_CP5_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dtie.h58 #define XCHAL_CP5_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dtie.h56 #define XCHAL_CP5_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dtie.h58 #define XCHAL_CP5_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dtie.h56 #define XCHAL_CP5_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dtie.h61 #define XCHAL_CP5_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dtie.h61 #define XCHAL_CP5_SA_SIZE 0 macro
/hal_xtensa-3.7.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dtie.h61 #define XCHAL_CP5_SA_SIZE 0 macro
/hal_xtensa-3.7.0/include/xtensa/config/
Dcore.h1108 # if XCHAL_CP5_SA_SIZE == 0
1166 # if XCHAL_CP5_SA_SIZE
1227 # if XCHAL_CP5_SA_SIZE
1306 #define XCHAL_CP5_SA_SIZE 0 macro