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Searched refs:reg (Results 1 – 5 of 5) sorted by relevance

/hal_xtensa-3.6.0/src/hal/
Dstate.c226 int xthal_read_extra(void *base, unsigned reg, unsigned *value)
228 if (reg&0x1000) {
229 switch(reg) {
233 return reg;
236 return reg;
239 return reg;
242 return reg;
245 return reg;
248 return reg;
256 int xthal_write_extra(void *base, unsigned reg, unsigned value)
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/hal_xtensa-3.6.0/include/xtensa/
Dxdm-regs.h408 int reg; member
419 regname(regdef_t* list, int reg) in regname() argument
422 while (list[i].reg != -1) { in regname()
423 if (list[i].reg == reg) in regname()
Dcore-macros.h460 static inline unsigned XTHAL_RER (unsigned int reg) in XTHAL_RER() argument
466 : "=a" (result) : "a" (reg) : "memory"); in XTHAL_RER()
471 static inline void XTHAL_WER (unsigned reg, unsigned value) in XTHAL_WER() argument
475 : : "a" (value), "a" (reg) : "memory"); in XTHAL_WER()
Dcoreasm.h637 .macro readsr reg suf ar
638 rsr.\reg\suf \ar
648 .macro writesr reg suf ar
649 wsr.\reg\suf \ar
659 .macro xchgsr reg suf ar
660 xsr.\reg\suf \ar
/hal_xtensa-3.6.0/include/xtensa/config/
Dcore.h1044 .irp reg,\aa,\ab,\ac,\ad
1045 .ifeq 0x\reg ; .set .Lnsaved_,.Lnsaved_+1 ; .endif
1048 .irp reg,\aa,\ab,\ac,\ad
1050 \inst \reg, \ptr, .Laofs_+\offset