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Searched refs:XCHAL_MMU_ASID_BITS (Results 1 – 13 of 13) sorted by relevance

/hal_xtensa-3.6.0/src/hal/
Dmisc.c105 const unsigned char Xthal_mmu_asid_bits = XCHAL_MMU_ASID_BITS;
/hal_xtensa-3.6.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h468 #define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h587 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h587 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h587 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h610 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ macro
/hal_xtensa-3.6.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h623 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ macro
/hal_xtensa-3.6.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h624 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h680 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h624 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx8ulp/xtensa/config/
Dcore-isa.h652 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ macro
/hal_xtensa-3.6.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h703 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h790 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ macro