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Searched refs:XCHAL_HAVE_XLT_CACHEATTR (Results 1 – 17 of 17) sorted by relevance

/hal_xtensa-3.6.0/src/hal/
Dset_region_translate.c126 #if XCHAL_HAVE_XLT_CACHEATTR || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY) in xthal_set_region_translation_raw()
127 # if XCHAL_HAVE_XLT_CACHEATTR in xthal_set_region_translation_raw()
294 #if XCHAL_HAVE_XLT_CACHEATTR in is_writeback()
400 #if XCHAL_HAVE_XLT_CACHEATTR || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY) in xthal_set_region_translation()
Dmisc.c94 const unsigned char Xthal_have_xlt_cacheattr = XCHAL_HAVE_XLT_CACHEATTR;
Dcache_asm.S247 #elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_S…
306 #elif XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
/hal_xtensa-3.6.0/include/xtensa/
Dxtruntime-core-state.h138 #if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
Dcacheattrasm.h38 …ne XCHAL_CA_8X512 (XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \
/hal_xtensa-3.6.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h460 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h580 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h580 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h580 #define XCHAL_HAVE_XLT_CACHEATTR 1 /* region prot. w/translation */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h603 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/hal_xtensa-3.6.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h616 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/hal_xtensa-3.6.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h618 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h673 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h618 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx8ulp/xtensa/config/
Dcore-isa.h645 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/hal_xtensa-3.6.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h696 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h783 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ macro