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Searched refs:XCHAL_HAVE_TLBS (Results 1 – 14 of 14) sorted by relevance

/hal_xtensa-3.6.0/src/hal/
Dmisc.c96 const unsigned char Xthal_have_tlbs = XCHAL_HAVE_TLBS;
112 #if XCHAL_HAVE_TLBS
169 const unsigned char Xthal_have_mmu = XCHAL_HAVE_TLBS;
/hal_xtensa-3.6.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h454 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h574 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h574 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h574 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h597 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/hal_xtensa-3.6.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h610 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/hal_xtensa-3.6.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h612 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h667 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h612 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx8ulp/xtensa/config/
Dcore-isa.h639 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/hal_xtensa-3.6.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h691 #define XCHAL_HAVE_TLBS 0 /* inverse of HAVE_CACHEATTR */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h777 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/hal_xtensa-3.6.0/include/xtensa/config/
Dcore.h902 #if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS >…