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Searched refs:XCHAL_HAVE_BE (Results 1 – 16 of 16) sorted by relevance

/hal_xtensa-3.6.0/src/hal/
Ddebug.c43 #if XCHAL_HAVE_BE
73 #if XCHAL_HAVE_BE in xthal_set_soft_break()
82 #if XCHAL_HAVE_BE in xthal_set_soft_break()
120 #if XCHAL_HAVE_BE in xthal_remove_soft_break()
158 #if XCHAL_HAVE_BE in xthal_inst_type()
291 #if XCHAL_HAVE_BE in xthal_branch_addr()
303 # if XCHAL_HAVE_BE in xthal_branch_addr()
312 #if XCHAL_HAVE_BE in xthal_branch_addr()
331 #if XCHAL_HAVE_BE in xthal_branch_addr()
396 #if XCHAL_HAVE_BE in xthal_get_npc()
[all …]
Ddisass.c61 # if XCHAL_HAVE_BE in xthal_disassemble_size()
Dcache_asm.S812 # if XCHAL_HAVE_BE
/hal_xtensa-3.6.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h51 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h51 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h51 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h51 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/hal_xtensa-3.6.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/hal_xtensa-3.6.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h51 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h51 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx8ulp/xtensa/config/
Dcore-isa.h49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/hal_xtensa-3.6.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ macro
/hal_xtensa-3.6.0/include/xtensa/config/
Dcore.h140 #if XCHAL_HAVE_BE
1369 #if XCHAL_HAVE_BE