1 /* TRAX register definitions 2 3 Copyright (c) 2006-2012 Tensilica Inc. 4 5 Permission is hereby granted, free of charge, to any person obtaining 6 a copy of this software and associated documentation files (the 7 "Software"), to deal in the Software without restriction, including 8 without limitation the rights to use, copy, modify, merge, publish, 9 distribute, sublicense, and/or sell copies of the Software, and to 10 permit persons to whom the Software is furnished to do so, subject to 11 the following conditions: 12 13 The above copyright notice and this permission notice shall be included 14 in all copies or substantial portions of the Software. 15 16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 17 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 19 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 20 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24 #ifndef _TRAX_REGISTERS_H_ 25 #define _TRAX_REGISTERS_H_ 26 27 #define SHOW 1 28 #define HIDE 0 29 30 #define RO 0 31 #define RW 1 32 33 /* TRAX Register Numbers (from possible range of 0..127) */ 34 #if 0 35 #define TRAXREG_ID 0 36 #define TRAXREG_CONTROL 1 37 #define TRAXREG_STATUS 2 38 #define TRAXREG_DATA 3 39 #define TRAXREG_ADDRESS 4 40 #define TRAXREG_TRIGGER 5 41 #define TRAXREG_MATCH 6 42 #define TRAXREG_DELAY 7 43 #define TRAXREG_STARTADDR 8 44 #define TRAXREG_ENDADDR 9 45 /* Internal use only (unpublished): */ 46 #define TRAXREG_P4CHANGE 16 47 #define TRAXREG_P4REV 17 48 #define TRAXREG_P4DATE 18 49 #define TRAXREG_P4TIME 19 50 #define TRAXREG_PDSTATUS 20 51 #define TRAXREG_PDDATA 21 52 #define TRAXREG_STOP_PC 22 53 #define TRAXREG_STOP_ICNT 23 54 #define TRAXREG_MSG_STATUS 24 55 #define TRAXREG_FSM_STATUS 25 56 #define TRAXREG_IB_STATUS 26 57 #define TRAXREG_MAX 27 58 #define TRAXREG_ITCTRL 96 59 #endif 60 /* The registers above match the NAR addresses. So, their values are used for NAR access */ 61 62 /* TRAX Register Fields */ 63 64 /* TRAX ID register fields: */ 65 #define TRAX_ID_PRODNO 0xf0000000 /* product number (0=TRAX) */ 66 #define TRAX_ID_PRODOPT 0x0f000000 /* product options */ 67 #define TRAX_ID_MIW64 0x08000000 /* opt: instruction width */ 68 #define TRAX_ID_AMTRAX 0x04000000 /* opt: collection of options, 69 internal (VER_2_0 or later)*/ 70 #define TRAX_ID_MAJVER(id) (((id) >> 20) & 0x0f) 71 #define TRAX_ID_MINVER(id) (((id) >> 17) & 0x07) 72 #define TRAX_ID_VER(id) ((TRAX_ID_MAJVER(id)<<4)|TRAX_ID_MINVER(id)) 73 #define TRAX_ID_STDCFG 0x00010000 /* standard config */ 74 #define TRAX_ID_CFGID 0x0000ffff /* TRAX configuration ID */ 75 #define TRAX_ID_MEMSHARED 0x00001000 /* Memshared option in TRAX */ 76 #define TRAX_ID_FROM_VER(ver) ((((ver) & 0xf0) << 16) | (((ver) & 0x7) << 17)) 77 /* Other TRAX ID register macros: */ 78 /* TRAX versions of interest (TRAX_ID_VER(), ie. MAJVER*16 + MINVER): */ 79 #define TRAX_VER_1_0 0x10 /* RA */ 80 #define TRAX_VER_1_1 0x11 /* RB thru RC-2010.1 */ 81 #define TRAX_VER_2_0 0x20 /* RC-2010.2, RD-2010.0, 82 RD-2011.1 */ 83 #define TRAX_VER_2_1 0x21 /* RC-2011.3 / RD-2011.2 and 84 later */ 85 #define TRAX_VER_3_0 0x30 /* RE-2012.0 */ 86 #define TRAX_VER_3_1 0x31 /* RE-2012.1 */ 87 #define TRAX_VER_HUAWEI_3 TRAX_VER_3_0 /* For Huawei, PRs: 25223, 25224 88 , 24880 */ 89 90 91 /* TRAX version 1.0 requires a couple software workarounds: */ 92 #define TRAX_ID_1_0_ERRATUM(id) (TRAX_ID_VER(id) == TRAX_VER_1_0) 93 /* TRAX version 2.0 requires software workaround for PR 22161: */ 94 #define TRAX_ID_MEMSZ_ERRATUM(id) (TRAX_ID_VER(id) == TRAX_VER_2_0) 95 96 /* TRAX Control register fields: */ 97 #define TRAX_CONTROL_TREN 0x00000001 98 #define TRAX_CONTROL_TRSTP 0x00000002 99 #define TRAX_CONTROL_PCMEN 0x00000004 100 #define TRAX_CONTROL_PTIEN 0x00000010 101 #define TRAX_CONTROL_CTIEN 0x00000020 102 #define TRAX_CONTROL_TMEN 0x00000080 /* 2.0+ */ 103 #define TRAX_CONTROL_CNTU 0x00000200 104 #define TRAX_CONTROL_BIEN 0x00000400 105 #define TRAX_CONTROL_BOEN 0x00000800 106 #define TRAX_CONTROL_TSEN 0x00000800 107 #define TRAX_CONTROL_SMPER 0x00007000 108 #define TRAX_CONTROL_SMPER_SHIFT 12 109 #define TRAX_CONTROL_PTOWT 0x00010000 110 #define TRAX_CONTROL_CTOWT 0x00020000 111 #define TRAX_CONTROL_PTOWS 0x00100000 112 #define TRAX_CONTROL_CTOWS 0x00200000 113 #define TRAX_CONTROL_ATID 0x7F000000 /* 2.0+, amtrax */ 114 #define TRAX_CONTROL_ATID_SHIFT 24 115 #define TRAX_CONTROL_ATEN 0x80000000 /* 2.0+, amtrax */ 116 117 #define TRAX_CONTROL_PTOWS_ER 0x00020000 /* For 3.0 */ 118 #define TRAX_CONTROL_CTOWT_ER 0x00100000 /* For 3.0 */ 119 120 #define TRAX_CONTROL_ITCTO 0x00400000 /* For 3.0 */ 121 #define TRAX_CONTROL_ITCTIA 0x00800000 /* For 3.0 */ 122 #define TRAX_CONTROL_ITATV 0x01000000 /* For 3.0 */ 123 124 125 /* TRAX Status register fields: */ 126 #define TRAX_STATUS_TRACT 0x00000001 127 #define TRAX_STATUS_TRIG 0x00000002 128 #define TRAX_STATUS_PCMTG 0x00000004 129 #define TRAX_STATUS_BUSY 0x00000008 /* ER ??? */ 130 #define TRAX_STATUS_PTITG 0x00000010 131 #define TRAX_STATUS_CTITG 0x00000020 132 #define TRAX_STATUS_MEMSZ 0x00001F00 133 #define TRAX_STATUS_MEMSZ_SHIFT 8 134 #define TRAX_STATUS_PTO 0x00010000 135 #define TRAX_STATUS_CTO 0x00020000 136 137 #define TRAX_STATUS_ITCTOA 0x00400000 /* For 3.0 */ 138 #define TRAX_STATUS_ITCTI 0x00800000 /* For 3.0 */ 139 #define TRAX_STATUS_ITATR 0x01000000 /* For 3.0 */ 140 141 142 /* TRAX Address register fields: */ 143 #define TRAX_ADDRESS_TWSAT 0x80000000 144 #define TRAX_ADDRESS_TWSAT_SHIFT 31 145 #define TRAX_ADDRESS_TOTALMASK 0x00FFFFFF 146 // !!! VUakiVU. added for new TRAX: 147 #define TRAX_ADDRESS_WRAPCNT 0x7FE00000 /* version ???... */ 148 #define TRAX_ADDRESS_WRAP_SHIFT 21 149 150 /* TRAX PCMatch register fields: */ 151 #define TRAX_PCMATCH_PCML 0x0000001F 152 #define TRAX_PCMATCH_PCML_SHIFT 0 153 #define TRAX_PCMATCH_PCMS 0x80000000 154 155 /* Compute trace ram buffer size (in bytes) from status register: */ 156 #define TRAX_MEM_SIZE(status) (1L << (((status) & TRAX_STATUS_MEMSZ) >> TRAX_STATUS_MEMSZ_SHIFT)) 157 158 #if 0 159 /* Describes a field within a register: */ 160 typedef struct { 161 const char* name; 162 // unsigned width; 163 // unsigned shift; 164 char width; 165 char shift; 166 char visible; /* 0 = internal use only, 1 = shown */ 167 char reserved; 168 } trax_regfield_t; 169 #endif 170 171 /* Describes a TRAX register: */ 172 typedef struct { 173 const char* name; 174 unsigned id; 175 char width; 176 char visible; 177 char writable; 178 char reserved; 179 //const trax_regfield_t * fieldset; 180 } trax_regdef_t; 181 182 183 extern const trax_regdef_t trax_reglist[]; 184 extern const signed char trax_readable_regs[]; 185 186 #ifdef __cplusplus 187 extern "C" { 188 #endif 189 190 /* Prototypes: */ 191 extern int trax_find_reg(char * regname, char **errmsg); 192 extern const char * trax_regname(int regno); 193 194 #ifdef __cplusplus 195 } 196 #endif 197 198 #endif /* _TRAX_REGISTERS_H_ */ 199 200
