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Searched refs:XCHAL_ICACHE_SIZE (Results 1 – 20 of 20) sorted by relevance

/hal_xtensa-3.5.0/include/xtensa/
Dcacheasm.h318 #if XCHAL_ICACHE_SIZE > 0
335 #if XCHAL_ICACHE_SIZE > 0
352 #if XCHAL_ICACHE_SIZE > 0
354 …cache_index_all iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, XCHAL_ICACHE_WAYS, \aa, \ab, \loop…
372 #if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
388 #if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
408 #if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
424 #if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
441 #if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
443 cache_index_all iiu, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240
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Dcore-macros.h107 #if XCHAL_ICACHE_SIZE > 0
115 #if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
/hal_xtensa-3.5.0/src/hal/
Dcache.c46 const unsigned int Xthal_icache_size = XCHAL_ICACHE_SIZE;
Dmem_ecc_parity.S60 #if XCHAL_ICACHE_LINEWIDTH < XCHAL_DCACHE_LINEWIDTH && XCHAL_ICACHE_SIZE > 0
160 # if XCHAL_ICACHE_SIZE || XCHAL_DCACHE_SIZE
189 # if XCHAL_ICACHE_SIZE && XCHAL_HAVE_ICACHE_TEST
Dcache_asm.S132 #if (!defined(XCHAL_HAVE_NX) || XCHAL_HAVE_NX == 0) &&XCHAL_ICACHE_SIZE > 0 && \
134 movi a4, XCHAL_ICACHE_SIZE*2 // size at which to use huge algorithm
141 movi a7, XCHAL_ICACHE_SIZE/XCHAL_ICACHE_LINESIZE // a7 = number of lines in dcache
142 movi a3, XCHAL_ICACHE_SIZE-XCHAL_ICACHE_LINESIZE // way index
145 movi a10, (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS) - 1
Dattribute.c231 # if XCHAL_ICACHE_SIZE == 0 && XCHAL_DCACHE_SIZE == 0 in xthal_set_region_attribute()
Ddebug.c109 #if XCHAL_ICACHE_SIZE > 0 in xthal_set_soft_break()
138 #if XCHAL_ICACHE_SIZE > 0 in xthal_remove_soft_break()
Dset_region_translate.c490 #if XCHAL_ICACHE_SIZE >0 in xthal_set_region_translation()
/hal_xtensa-3.5.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h162 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h244 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h244 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h244 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h244 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/hal_xtensa-3.5.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h237 #define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h296 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ macro
/hal_xtensa-3.5.0/zephyr/soc/nxp_imx8/xtensa/config/
Dcore-isa.h217 #define XCHAL_ICACHE_SIZE 32768 /* I-cache size in bytes or 0 */ macro
/hal_xtensa-3.5.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h217 #define XCHAL_ICACHE_SIZE 32768 /* I-cache size in bytes or 0 */ macro
/hal_xtensa-3.5.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h289 #define XCHAL_ICACHE_SIZE 32768 /* I-cache size in bytes or 0 */ macro
/hal_xtensa-3.5.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h294 #define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ macro
/hal_xtensa-3.5.0/include/xtensa/config/
Dcore.h107 XCHAL_ICACHE_SIZE != 0 && XCHAL_HAVE_PIF /*covers also AXI/AHB*/ && \