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Searched refs:XCHAL_DCACHE_IS_COHERENT (Results 1 – 14 of 14) sorted by relevance

/hal_xtensa-3.5.0/src/hal/
Dcoherence.c41 #if XCHAL_HAVE_EXTERN_REGS && XCHAL_DCACHE_IS_COHERENT in xthal_cache_coherence_optout()
/hal_xtensa-3.5.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h166 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/hal_xtensa-3.5.0/include/xtensa/
Dcacheasm.h508 #if XCHAL_DCACHE_IS_COHERENT
542 #if XCHAL_DCACHE_IS_COHERENT
/hal_xtensa-3.5.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h248 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h248 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h248 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h248 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/hal_xtensa-3.5.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h241 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h302 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/hal_xtensa-3.5.0/zephyr/soc/nxp_imx8/xtensa/config/
Dcore-isa.h221 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/hal_xtensa-3.5.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h221 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/hal_xtensa-3.5.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h295 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/hal_xtensa-3.5.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h300 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ macro
/hal_xtensa-3.5.0/include/xtensa/config/
Dcore.h841 XCHAL_DCACHE_IS_COHERENT || \
846 #if XCHAL_DCACHE_IS_COHERENT