Searched refs:XCHAL_CP0_SA_SIZE (Results 1 – 14 of 14) sorted by relevance
| /hal_xtensa-3.5.0/include/xtensa/ |
| D | xtruntime-core-state.h | 177 #if XCHAL_CP0_SA_SIZE > 0
178 STRUCT_AFIELD_A(char,1,XCHAL_CP0_SA_ALIGN,CS_SA_,cp0,XCHAL_CP0_SA_SIZE)
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| D | xtruntime-frames.h | 120 STRUCT_AFIELD (long,4,UEXC_,cp0, XCHAL_CP0_SA_SIZE / 4)
126 #define ALIGNPAD ((2 + XCHAL_HAVE_MAC16*2 + ((XCHAL_CP0_SA_SIZE%16)/4) + ((XCHAL_CP1_SA_SIZE%16)/4…
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| /hal_xtensa-3.5.0/zephyr/soc/dc233c/xtensa/config/ |
| D | tie.h | 48 #define XCHAL_CP0_SA_SIZE 0 macro
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| /hal_xtensa-3.5.0/zephyr/soc/intel_apl_adsp/xtensa/config/ |
| D | tie.h | 50 #define XCHAL_CP0_SA_SIZE 0 macro
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| /hal_xtensa-3.5.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/ |
| D | tie.h | 50 #define XCHAL_CP0_SA_SIZE 0 macro
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| /hal_xtensa-3.5.0/zephyr/soc/mt8195_adsp/xtensa/config/ |
| D | tie.h | 50 #define XCHAL_CP0_SA_SIZE 0 macro
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| /hal_xtensa-3.5.0/src/hal/ |
| D | state.c | 40 XCHAL_CP0_SA_SIZE,
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| /hal_xtensa-3.5.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/ |
| D | tie.h | 50 #define XCHAL_CP0_SA_SIZE 0 macro
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| /hal_xtensa-3.5.0/zephyr/soc/nxp_imx8/xtensa/config/ |
| D | tie.h | 48 #define XCHAL_CP0_SA_SIZE 0 macro
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| /hal_xtensa-3.5.0/zephyr/soc/mimx8ml8/xtensa/config/ |
| D | tie.h | 48 #define XCHAL_CP0_SA_SIZE 0 macro
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| /hal_xtensa-3.5.0/zephyr/soc/intel_cnl_adsp/xtensa/config/ |
| D | tie.h | 45 #define XCHAL_CP0_SA_SIZE 72 /* size of state save area */ macro
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| /hal_xtensa-3.5.0/zephyr/soc/intel_icl_adsp/xtensa/config/ |
| D | tie.h | 45 #define XCHAL_CP0_SA_SIZE 72 /* size of state save area */ macro
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| /hal_xtensa-3.5.0/zephyr/soc/intel_tgl_adsp/xtensa/config/ |
| D | tie.h | 45 #define XCHAL_CP0_SA_SIZE 72 /* size of state save area */ macro
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| /hal_xtensa-3.5.0/include/xtensa/config/ |
| D | core.h | 1088 # if XCHAL_CP0_SA_SIZE == 0
1136 # if XCHAL_CP0_SA_SIZE
1197 # if XCHAL_CP0_SA_SIZE
1296 #define XCHAL_CP0_SA_SIZE 0 macro
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