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/hal_xtensa-3.4.0/src/hal/
Ddebug_hndlr.S89 j 3f
99 j 3f
110 j 3f
121 j 3f
127 j 3f
131 j 3f
Dinterrupts.c351 int i, j;
359 for( j = 0; j < 16; j++ )
360 Xthal_vpri_enablemap[i][j] = XCHAL_INTLEVEL15_ANDBELOW_MASK
361 & ~Xthal_intlevel_andbelow_mask[i - (j < default_vpri && i > 0)];
364 for( j = 0; j < 16; j++ )
365 Xthal_vpri_resolvemap[i-1][j] = 0;
Dwindowspill_asm.S214 j .Linvalid_window // else it's an invalid window!
229 j .Lspill_loop
252 j .Lspill_loop
282 j .Lspill_loop
Dmem_ecc_parity.S185 j .L_inject_done
209 j .L_inject_done
232 j .L_inject_done
Dint_asm.S250 j xthal_set_vpri_nw_common // set vpri to a2
328 j xthal_set_vpri_common1 // set vpri to a2
346 j xthal_set_vpri_common1
Dcache_asm.S105 7: j.l xthal_dcache_region_\name + ABI_ENTRY_MINSIZE, a4
170 7: j.l xthal_icache_region_\name + ABI_ENTRY_MINSIZE, a4
845j 1f ; .align 8 ; 1: xsr.prefctl a2 ; isync // ensure XSR.PREFCTL;ISYNC wholly within an icache li…
880j 1f ; .align 8 ; 1: xsr.prefctl a2 ; isync // ensure XSR.PREFCTL;ISYNC wholly within an icache li…
Dmpu.c564 int j; in needed_entries_exist() local
577 for (j = i; j < XCHAL_MPU_ENTRIES; j++) in needed_entries_exist()
578 if (last == XTHAL_MPU_ENTRY_GET_VSTARTADDR(fg[j])) in needed_entries_exist()
581 for (k = i; k <= j; k++) in needed_entries_exist()
Dmemcopy.S126 j .Lcommon // go to common code for memcpy+bcopy
161 j .Ldstaligned
/hal_xtensa-3.4.0/include/xtensa/
Dmpuasm.h56 j 1f
70 j 3f
85 j 2b
Dcacheattrasm.h196 j \label // macro not applicable, assume caches always enabled
302 j 3f
414 j 1f
Doverlay_os_asm.h116 j .L4 // PC is in VMA range
Dcacheasm.h943 j .Ldsw1
Dcoreasm.h326 j 1f
/hal_xtensa-3.4.0/include/xtensa/config/
Dcore.h1139 j 90f
1145 j 90f
1151 j 90f
1157 j 90f
1163 j 90f
1169 j 90f
1175 j 90f
1181 j 90f
1200 j 90f
1206 j 90f
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