1 /* 2 xtensa/hal.h -- contains a definition of the Core HAL interface 3 4 All definitions in this header file are independent of any specific 5 Xtensa processor configuration. Thus software (eg. OS, application, 6 etc) can include this header file and be compiled into configuration- 7 independent objects that can be distributed and eventually linked 8 to the HAL library (libhal.a) to create a configuration-specific 9 final executable. 10 11 Certain definitions, however, are release/version-specific -- such as 12 the XTHAL_RELEASE_xxx macros (or additions made in later versions). 13 14 15 $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/target-os-src/hal.h.tpp#1 $ 16 17 Copyright (c) 1999-2015 Cadence Design Systems, Inc. 18 19 Permission is hereby granted, free of charge, to any person obtaining 20 a copy of this software and associated documentation files (the 21 "Software"), to deal in the Software without restriction, including 22 without limitation the rights to use, copy, modify, merge, publish, 23 distribute, sublicense, and/or sell copies of the Software, and to 24 permit persons to whom the Software is furnished to do so, subject to 25 the following conditions: 26 27 The above copyright notice and this permission notice shall be included 28 in all copies or substantial portions of the Software. 29 30 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 31 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 32 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 33 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 34 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 35 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 36 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 37 */ 38 39 #ifndef XTENSA_HAL_H 40 #define XTENSA_HAL_H 41 42 43 /**************************************************************************** 44 Definitions Useful for Any Code, USER or PRIVILEGED 45 ****************************************************************************/ 46 47 48 /*---------------------------------------------------------------------- 49 Constant Definitions (shared with assembly) 50 ----------------------------------------------------------------------*/ 51 52 /* 53 * Software (Xtensa Tools) version information. Not configuration-specific! 54 * 55 * NOTE: "release" is a misnomer here, these are really product "version" 56 * numbers. A "release" is a collection of product versions 57 * made available at once (together) to customers. 58 * In the past, release and version names all matched in T####.# form, 59 * making the distinction irrelevant. This is no longer the case. 60 */ 61 #define XTHAL_RELEASE_MAJOR 12000 62 #define XTHAL_RELEASE_MINOR 8 63 #define XTHAL_RELEASE_NAME "12.0.8" 64 #define XTHAL_REL_12 1 65 #define XTHAL_REL_12_0 1 66 #define XTHAL_REL_12_0_8 1 67 68 /* HAL version numbers (these names are for backward compatibility): */ 69 #define XTHAL_MAJOR_REV XTHAL_RELEASE_MAJOR 70 #define XTHAL_MINOR_REV XTHAL_RELEASE_MINOR 71 /* 72 * A bit of software release/version history on values of XTHAL_{MAJOR,MINOR}_REV: 73 * 74 * SW Version MAJOR MINOR Comment 75 * ======= ===== ===== ======= 76 * T1015.n n/a n/a (HAL not yet available) 77 * T1020.{0,1,2} 0 1 (HAL beta) 78 * T1020.{3,4} 0 2 First release. 79 * T1020.n (n>4) 0 2 or >3 (TBD) 80 * T1030.0 0 1 (HAL beta) 81 * T1030.{1,2} 0 3 Equivalent to first release. 82 * T1030.n (n>=3) 0 >= 3 (TBD) 83 * T1040.n 1040 n Full CHAL available from T1040.2 84 * T1050.n 1050 n . 85 * 6.0.n 6000 n Xtensa Tools v6 (RA-200x.n) 86 * 7.0.n 7000 n Xtensa Tools v7 (RB-200x.n) 87 * 7.1.n 7010 n Xtensa Tools v7.1 (RB-200x.(n+2)) 88 * 8.0.n 8000 n Xtensa Tools v8 (RC-20xx.n) 89 * 9.0.n 9000 n Xtensa Tools v9 (RD-201x.n) 90 * 10.0.n 10000 n Xtensa Tools v10 (RE-201x.n) 91 * 92 * 93 * Note: there is a distinction between the software version with 94 * which something is compiled (accessible using XTHAL_RELEASE_* macros) 95 * and the software version with which the HAL library was compiled 96 * (accessible using Xthal_release_* global variables). This 97 * distinction is particularly relevant for vendors that distribute 98 * configuration-independent binaries (eg. an OS), where their customer 99 * might link it with a HAL of a different Xtensa software version. 100 * In this case, it may be appropriate for the OS to verify at run-time 101 * whether XTHAL_RELEASE_* and Xthal_release_* are compatible. 102 * [Guidelines as to which version is compatible with which are not 103 * currently provided explicitly, but might be inferred from reading 104 * OSKit documentation for all releases -- compatibility is also highly 105 * dependent on which HAL features are used. Each version is usually 106 * backward compatible, with very few exceptions if any.] 107 */ 108 109 /* Version comparison operators (among major/minor pairs): */ 110 #define XTHAL_REL_GE(maja,mina, majb,minb) ((maja) > (majb) || \ 111 ((maja) == (majb) && (mina) >= (minb))) 112 #define XTHAL_REL_GT(maja,mina, majb,minb) ((maja) > (majb) || \ 113 ((maja) == (majb) && (mina) > (minb))) 114 #define XTHAL_REL_LE(maja,mina, majb,minb) ((maja) < (majb) || \ 115 ((maja) == (majb) && (mina) <= (minb))) 116 #define XTHAL_REL_LT(maja,mina, majb,minb) ((maja) < (majb) || \ 117 ((maja) == (majb) && (mina) < (minb))) 118 #define XTHAL_REL_EQ(maja,mina, majb,minb) ((maja) == (majb) && (mina) == (minb)) 119 120 /* Fuzzy (3-way) logic operators: */ 121 #define XTHAL_MAYBE -1 /* 0=NO, 1=YES, -1=MAYBE */ 122 #define XTHAL_FUZZY_AND(a,b) (((a)==0 || (b)==0) ? 0 : ((a)==1 && (b)==1) ? 1 : XTHAL_MAYBE) 123 #define XTHAL_FUZZY_OR(a,b) (((a)==1 || (b)==1) ? 1 : ((a)==0 && (b)==0) ? 0 : XTHAL_MAYBE) 124 #define XTHAL_FUZZY_NOT(a) (((a)==0 || (a)==1) ? (1-(a)) : XTHAL_MAYBE) 125 126 127 /* 128 * Architectural limit, independent of configuration: 129 */ 130 #define XTHAL_MAX_CPS 8 /* max number of coprocessors (0..7) */ 131 132 /* Misc: */ 133 #define XTHAL_LITTLEENDIAN 0 134 #define XTHAL_BIGENDIAN 1 135 136 137 138 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) 139 #ifdef __cplusplus 140 extern "C" { 141 #endif 142 143 /*---------------------------------------------------------------------- 144 HAL 145 ----------------------------------------------------------------------*/ 146 147 /* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */ 148 extern const unsigned int Xthal_rev_no; 149 150 151 /*---------------------------------------------------------------------- 152 Optional/Custom Processor State 153 ----------------------------------------------------------------------*/ 154 155 /* save & restore the extra processor state */ 156 extern void xthal_save_extra(void *base); 157 extern void xthal_restore_extra(void *base); 158 159 extern void xthal_save_cpregs(void *base, int); 160 extern void xthal_restore_cpregs(void *base, int); 161 /* versions specific to each coprocessor id */ 162 extern void xthal_save_cp0(void *base); 163 extern void xthal_save_cp1(void *base); 164 extern void xthal_save_cp2(void *base); 165 extern void xthal_save_cp3(void *base); 166 extern void xthal_save_cp4(void *base); 167 extern void xthal_save_cp5(void *base); 168 extern void xthal_save_cp6(void *base); 169 extern void xthal_save_cp7(void *base); 170 extern void xthal_restore_cp0(void *base); 171 extern void xthal_restore_cp1(void *base); 172 extern void xthal_restore_cp2(void *base); 173 extern void xthal_restore_cp3(void *base); 174 extern void xthal_restore_cp4(void *base); 175 extern void xthal_restore_cp5(void *base); 176 extern void xthal_restore_cp6(void *base); 177 extern void xthal_restore_cp7(void *base); 178 /* pointers to each of the functions above */ 179 extern void* Xthal_cpregs_save_fn[XTHAL_MAX_CPS]; 180 extern void* Xthal_cpregs_restore_fn[XTHAL_MAX_CPS]; 181 /* similarly for non-windowed ABI (may be same or different) */ 182 extern void* Xthal_cpregs_save_nw_fn[XTHAL_MAX_CPS]; 183 extern void* Xthal_cpregs_restore_nw_fn[XTHAL_MAX_CPS]; 184 185 /*extern void xthal_save_all_extra(void *base);*/ 186 /*extern void xthal_restore_all_extra(void *base);*/ 187 188 /* space for processor state */ 189 extern const unsigned int Xthal_extra_size; 190 extern const unsigned int Xthal_extra_align; 191 extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS]; 192 extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS]; 193 extern const unsigned int Xthal_all_extra_size; 194 extern const unsigned int Xthal_all_extra_align; 195 /* coprocessor names */ 196 extern const char * const Xthal_cp_names[XTHAL_MAX_CPS]; 197 198 /* initialize the extra processor */ 199 /*extern void xthal_init_extra(void);*/ 200 /* initialize the TIE coprocessor */ 201 /*extern void xthal_init_cp(int);*/ 202 203 /* initialize the extra processor */ 204 extern void xthal_init_mem_extra(void *); 205 /* initialize the TIE coprocessor */ 206 extern void xthal_init_mem_cp(void *, int); 207 208 /* the number of TIE coprocessors contiguous from zero (for Tor2) */ 209 extern const unsigned int Xthal_num_coprocessors; 210 211 /* actual number of coprocessors */ 212 extern const unsigned char Xthal_cp_num; 213 /* index of highest numbered coprocessor, plus one */ 214 extern const unsigned char Xthal_cp_max; 215 /* index of highest allowed coprocessor number, per cfg, plus one */ 216 /*extern const unsigned char Xthal_cp_maxcfg;*/ 217 /* bitmask of which coprocessors are present */ 218 extern const unsigned int Xthal_cp_mask; 219 220 /* read & write extra state register */ 221 /*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/ 222 /*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/ 223 224 /* read & write a TIE coprocessor register */ 225 /*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/ 226 /*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/ 227 228 /* return coprocessor number based on register */ 229 /*extern int xthal_which_cp(unsigned reg);*/ 230 231 232 /*---------------------------------------------------------------------- 233 Register Windows 234 ----------------------------------------------------------------------*/ 235 236 /* number of registers in register window */ 237 extern const unsigned int Xthal_num_aregs; 238 extern const unsigned char Xthal_num_aregs_log2; 239 240 241 /*---------------------------------------------------------------------- 242 Cache 243 ----------------------------------------------------------------------*/ 244 245 /* size of the cache lines in log2(bytes) */ 246 extern const unsigned char Xthal_icache_linewidth; 247 extern const unsigned char Xthal_dcache_linewidth; 248 /* size of the cache lines in bytes (2^linewidth) */ 249 extern const unsigned short Xthal_icache_linesize; 250 extern const unsigned short Xthal_dcache_linesize; 251 252 /* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */ 253 extern const unsigned int Xthal_icache_size; 254 extern const unsigned int Xthal_dcache_size; 255 /* cache features */ 256 extern const unsigned char Xthal_dcache_is_writeback; 257 258 /* cache region operations*/ 259 extern void xthal_icache_region_invalidate( void *addr, unsigned size ); 260 extern void xthal_dcache_region_invalidate( void *addr, unsigned size ); 261 extern void xthal_dcache_region_writeback( void *addr, unsigned size ); 262 extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size ); 263 264 #ifndef XTHAL_USE_CACHE_MACROS 265 /* cache line operations*/ 266 extern void xthal_icache_line_invalidate(void *addr); 267 extern void xthal_dcache_line_invalidate(void *addr); 268 extern void xthal_dcache_line_writeback(void *addr); 269 extern void xthal_dcache_line_writeback_inv(void *addr); 270 /* sync icache and memory */ 271 extern void xthal_icache_sync( void ); 272 /* sync dcache and memory */ 273 extern void xthal_dcache_sync( void ); 274 #endif 275 276 /* get/set number of icache ways enabled */ 277 extern unsigned int xthal_icache_get_ways(void); 278 extern void xthal_icache_set_ways(unsigned int ways); 279 /* get/set number of dcache ways enabled */ 280 extern unsigned int xthal_dcache_get_ways(void); 281 extern void xthal_dcache_set_ways(unsigned int ways); 282 283 /* coherency (low-level -- not normally called directly) */ 284 extern void xthal_cache_coherence_on( void ); 285 extern void xthal_cache_coherence_off( void ); 286 /* coherency (high-level) */ 287 extern void xthal_cache_coherence_optin( void ); 288 extern void xthal_cache_coherence_optout( void ); 289 290 /* 291 * Cache prefetch control. 292 * The parameter to xthal_set_cache_prefetch() contains both 293 * a PREFCTL register value and a mask of which bits to actually modify. 294 * This allows easily combining field macros (below) by ORing, 295 * leaving unspecified fields unmodified. 296 * 297 * For backward compatibility with the older version of this routine 298 * (that took 15-bit value and mask in a 32-bit parameter, for pre-RF 299 * cores with only the lower 15 bits of PREFCTL defined), the 32-bit 300 * value and mask are staggered as follows in a 64-bit parameter: 301 * param[63:48] are PREFCTL[31:16] if param[31] is set 302 * param[47:32] are mask[31:16] if param[31] is set 303 * param[31] is set if mask is used, 0 if not 304 * param[31:16] are mask[15:0] if param[31] is set 305 * param[31:16] are PREFCTL[31:16] if param[31] is clear 306 * param[15:0] are PREFCTL[15:0] 307 * 308 * Limitation: PREFCTL register bit 31 cannot be set without masking, 309 * and bit 15 must always be set when using masking, so it is hoped that 310 * these two bits will remain reserved, read-as-zero in PREFCTL. 311 */ 312 #define XTHAL_PREFETCH_ENABLE -1 /* enable inst+data prefetch */ 313 #define XTHAL_PREFETCH_DISABLE 0xFFFF0000 /* disab inst+data prefetch*/ 314 #define XTHAL_DCACHE_PREFETCH(n) (0x800F0000+((n)&0xF)) /* data-side */ 315 #define XTHAL_DCACHE_PREFETCH_OFF XTHAL_DCACHE_PREFETCH(0) /* disable */ 316 #define XTHAL_DCACHE_PREFETCH_LOW XTHAL_DCACHE_PREFETCH(4) /* less aggr.*/ 317 #define XTHAL_DCACHE_PREFETCH_MEDIUM XTHAL_DCACHE_PREFETCH(5) /* mid aggr. */ 318 #define XTHAL_DCACHE_PREFETCH_HIGH XTHAL_DCACHE_PREFETCH(8) /* more aggr.*/ 319 #define XTHAL_DCACHE_PREFETCH_L1_OFF 0x90000000 /* to prefetch buffers*/ 320 #define XTHAL_DCACHE_PREFETCH_L1 0x90001000 /* direct to L1 dcache*/ 321 #define XTHAL_ICACHE_PREFETCH(n) (0x80F00000+(((n)&0xF)<<4)) /* i-side */ 322 #define XTHAL_ICACHE_PREFETCH_OFF XTHAL_ICACHE_PREFETCH(0) /* disable */ 323 #define XTHAL_ICACHE_PREFETCH_LOW XTHAL_ICACHE_PREFETCH(4) /* less aggr.*/ 324 #define XTHAL_ICACHE_PREFETCH_MEDIUM XTHAL_ICACHE_PREFETCH(5) /* mid aggr. */ 325 #define XTHAL_ICACHE_PREFETCH_HIGH XTHAL_ICACHE_PREFETCH(8) /* more aggr.*/ 326 #define XTHAL_ICACHE_PREFETCH_L1_OFF 0xA0000000 /* (not implemented) */ 327 #define XTHAL_ICACHE_PREFETCH_L1 0xA0002000 /* (not implemented) */ 328 #define _XTHAL_PREFETCH_BLOCKS(n) ((n)<0?0:(n)<5?(n):(n)<15?((n)>>1)+2:9) 329 #define XTHAL_PREFETCH_BLOCKS(n) (0x0000000F80000000ULL + \ 330 (((unsigned long long)_XTHAL_PREFETCH_BLOCKS(n))<<48)) 331 332 extern int xthal_get_cache_prefetch( void ); 333 extern int xthal_set_cache_prefetch( int ); 334 extern int xthal_set_cache_prefetch_long( unsigned long long ); 335 /* Only use the new extended function from now on: */ 336 #define xthal_set_cache_prefetch xthal_set_cache_prefetch_long 337 #define xthal_set_cache_prefetch_nw xthal_set_cache_prefetch_long_nw 338 339 340 /*---------------------------------------------------------------------- 341 Debug 342 ----------------------------------------------------------------------*/ 343 344 /* 1 if debug option configured, 0 if not: */ 345 extern const int Xthal_debug_configured; 346 347 /* Set (plant) and remove software breakpoint, both synchronizing cache: */ 348 extern unsigned int xthal_set_soft_break(void *addr); 349 extern void xthal_remove_soft_break(void *addr, unsigned int); 350 351 352 /*---------------------------------------------------------------------- 353 Disassembler 354 ----------------------------------------------------------------------*/ 355 356 /* Max expected size of the return buffer for a disassembled instruction (hint only): */ 357 #define XTHAL_DISASM_BUFSIZE 80 358 359 /* Disassembly option bits for selecting what to return: */ 360 #define XTHAL_DISASM_OPT_ADDR 0x0001 /* display address */ 361 #define XTHAL_DISASM_OPT_OPHEX 0x0002 /* display opcode bytes in hex */ 362 #define XTHAL_DISASM_OPT_OPCODE 0x0004 /* display opcode name (mnemonic) */ 363 #define XTHAL_DISASM_OPT_PARMS 0x0008 /* display parameters */ 364 #define XTHAL_DISASM_OPT_ALL 0x0FFF /* display everything */ 365 366 /* routine to get a string for the disassembled instruction */ 367 extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr, 368 char *buffer, unsigned buflen, unsigned options ); 369 370 /* routine to get the size of the next instruction. Returns 0 for 371 illegal instruction */ 372 extern int xthal_disassemble_size( unsigned char *instr_buf ); 373 374 375 /*---------------------------------------------------------------------- 376 Instruction/Data RAM/ROM Access 377 ----------------------------------------------------------------------*/ 378 379 extern void* xthal_memcpy(void *dst, const void *src, unsigned len); 380 extern void* xthal_bcopy(const void *src, void *dst, unsigned len); 381 382 383 /*---------------------------------------------------------------------- 384 MP Synchronization 385 ----------------------------------------------------------------------*/ 386 387 extern int xthal_compare_and_set( int *addr, int test_val, int compare_val ); 388 389 /*extern const char Xthal_have_s32c1i;*/ 390 391 392 /*---------------------------------------------------------------------- 393 Miscellaneous 394 ----------------------------------------------------------------------*/ 395 396 extern const unsigned int Xthal_release_major; 397 extern const unsigned int Xthal_release_minor; 398 extern const char * const Xthal_release_name; 399 extern const char * const Xthal_release_internal; 400 401 extern const unsigned char Xthal_memory_order; 402 extern const unsigned char Xthal_have_windowed; 403 extern const unsigned char Xthal_have_density; 404 extern const unsigned char Xthal_have_booleans; 405 extern const unsigned char Xthal_have_loops; 406 extern const unsigned char Xthal_have_nsa; 407 extern const unsigned char Xthal_have_minmax; 408 extern const unsigned char Xthal_have_sext; 409 extern const unsigned char Xthal_have_clamps; 410 extern const unsigned char Xthal_have_mac16; 411 extern const unsigned char Xthal_have_mul16; 412 extern const unsigned char Xthal_have_fp; 413 extern const unsigned char Xthal_have_speculation; 414 extern const unsigned char Xthal_have_threadptr; 415 416 extern const unsigned char Xthal_have_pif; 417 extern const unsigned short Xthal_num_writebuffer_entries; 418 419 extern const unsigned int Xthal_build_unique_id; 420 /* Version info for hardware targeted by software upgrades: */ 421 extern const unsigned int Xthal_hw_configid0; 422 extern const unsigned int Xthal_hw_configid1; 423 extern const unsigned int Xthal_hw_release_major; 424 extern const unsigned int Xthal_hw_release_minor; 425 extern const char * const Xthal_hw_release_name; 426 extern const char * const Xthal_hw_release_internal; 427 428 /* Clear any remnant code-dependent state (i.e. clear loop count regs). */ 429 extern void xthal_clear_regcached_code( void ); 430 431 #ifdef __cplusplus 432 } 433 #endif 434 #endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ 435 436 437 438 439 440 /**************************************************************************** 441 Definitions Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 442 ****************************************************************************/ 443 444 445 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 446 447 /*---------------------------------------------------------------------- 448 Constant Definitions (shared with assembly) 449 ----------------------------------------------------------------------*/ 450 451 /* 452 * Architectural limits, independent of configuration. 453 * Note that these are ISA-defined limits, not micro-architecture implementation 454 * limits enforced by the Xtensa Processor Generator (which may be stricter than 455 * these below). 456 */ 457 #define XTHAL_MAX_INTERRUPTS 32 /* max number of interrupts (0..31) */ 458 #define XTHAL_MAX_INTLEVELS 16 /* max number of interrupt levels (0..15) */ 459 /* (as of T1040, implementation limit is 7: 0..6) */ 460 #define XTHAL_MAX_TIMERS 4 /* max number of timers (CCOMPARE0..CCOMPARE3) */ 461 /* (as of T1040, implementation limit is 3: 0..2) */ 462 463 /* Interrupt types: */ 464 #define XTHAL_INTTYPE_UNCONFIGURED 0 465 #define XTHAL_INTTYPE_SOFTWARE 1 466 #define XTHAL_INTTYPE_EXTERN_EDGE 2 467 #define XTHAL_INTTYPE_EXTERN_LEVEL 3 468 #define XTHAL_INTTYPE_TIMER 4 469 #define XTHAL_INTTYPE_NMI 5 470 #define XTHAL_INTTYPE_WRITE_ERROR 6 471 #define XTHAL_INTTYPE_PROFILING 7 472 #define XTHAL_INTTYPE_IDMA_DONE 8 473 #define XTHAL_INTTYPE_IDMA_ERR 9 474 #define XTHAL_INTTYPE_GS_ERR 10 475 #define XTHAL_INTTYPE_SG_ERR 10 /* backward compatibility name - deprecated */ 476 #define XTHAL_MAX_INTTYPES 11 /* number of interrupt types */ 477 478 /* Timer related: */ 479 #define XTHAL_TIMER_UNCONFIGURED -1 /* Xthal_timer_interrupt[] value for non-existent timers */ 480 #define XTHAL_TIMER_UNASSIGNED XTHAL_TIMER_UNCONFIGURED /* (for backwards compatibility only) */ 481 482 /* Local Memory ECC/Parity: */ 483 #define XTHAL_MEMEP_PARITY 1 484 #define XTHAL_MEMEP_ECC 2 485 /* Flags parameter to xthal_memep_inject_error(): */ 486 #define XTHAL_MEMEP_F_LOCAL 0 /* local memory (default) */ 487 #define XTHAL_MEMEP_F_DCACHE_DATA 4 /* data cache data */ 488 #define XTHAL_MEMEP_F_DCACHE_TAG 5 /* data cache tag */ 489 #define XTHAL_MEMEP_F_ICACHE_DATA 6 /* instruction cache data */ 490 #define XTHAL_MEMEP_F_ICACHE_TAG 7 /* instruction cache tag */ 491 #define XTHAL_MEMEP_F_CORRECTABLE 16 /* inject correctable error 492 (default is non-corr.) */ 493 494 495 /* Access Mode bits (tentative): */ /* bit abbr unit short_name PPC equ - Description */ 496 #define XTHAL_AMB_EXCEPTION 0 /* 001 E EX fls: EXception none 497 exception on any access (aka "illegal") */ 498 #define XTHAL_AMB_HITCACHE 1 /* 002 C CH fls: use Cache on Hit ~(I CI) 499 [or H HC] way from tag match; 500 [or U UC] (ISA: same except Isolate case) */ 501 #define XTHAL_AMB_ALLOCATE 2 /* 004 A AL fl?: ALlocate none 502 [or F FI fill] refill cache on miss, way from LRU 503 (ISA: Read/Write Miss Refill) */ 504 #define XTHAL_AMB_WRITETHRU 3 /* 008 W WT --s: WriteThrough W WT 505 store immediately to memory (ISA: same) */ 506 #define XTHAL_AMB_ISOLATE 4 /* 010 I IS fls: ISolate none 507 use cache regardless of hit-vs-miss, 508 way from vaddr (ISA: use-cache-on-miss+hit) */ 509 #define XTHAL_AMB_GUARD 5 /* 020 G GU ?l?: GUard G * 510 non-speculative; spec/replay refs not permitted */ 511 #define XTHAL_AMB_COHERENT 6 /* 040 M MC ?ls: Mem/MP Coherent M 512 on read, other CPU/bus-master may need to supply data; 513 on write, maybe redirect to or flush other CPU dirty line; etc */ 514 #if 0 515 #define XTHAL_AMB_BUFFERABLE x /* 000 B BU --s: BUfferable ? 516 write response may return earlier than from final destination */ 517 #define XTHAL_AMB_ORDERED x /* 000 O OR fls: ORdered G * 518 mem accesses cannot be out of order */ 519 #define XTHAL_AMB_FUSEWRITES x /* 000 F FW --s: FuseWrites none 520 allow combining/merging/coalescing multiple writes 521 (to same datapath data unit) into one 522 (implied by writeback) */ 523 #define XTHAL_AMB_TRUSTED x /* 000 T TR ?l?: TRusted none 524 memory will not bus error (if it does, 525 handle as fatal imprecise interrupt) */ 526 #define XTHAL_AMB_PREFETCH x /* 000 P PR fl?: PRefetch none 527 on refill, read line+1 into prefetch buffers */ 528 #define XTHAL_AMB_STREAM x /* 000 S ST ???: STreaming none 529 access one of N stream buffers */ 530 #endif /*0*/ 531 532 #define XTHAL_AM_EXCEPTION (1<<XTHAL_AMB_EXCEPTION) 533 #define XTHAL_AM_HITCACHE (1<<XTHAL_AMB_HITCACHE) 534 #define XTHAL_AM_ALLOCATE (1<<XTHAL_AMB_ALLOCATE) 535 #define XTHAL_AM_WRITETHRU (1<<XTHAL_AMB_WRITETHRU) 536 #define XTHAL_AM_ISOLATE (1<<XTHAL_AMB_ISOLATE) 537 #define XTHAL_AM_GUARD (1<<XTHAL_AMB_GUARD) 538 #define XTHAL_AM_COHERENT (1<<XTHAL_AMB_COHERENT) 539 #if 0 540 #define XTHAL_AM_BUFFERABLE (1<<XTHAL_AMB_BUFFERABLE) 541 #define XTHAL_AM_ORDERED (1<<XTHAL_AMB_ORDERED) 542 #define XTHAL_AM_FUSEWRITES (1<<XTHAL_AMB_FUSEWRITES) 543 #define XTHAL_AM_TRUSTED (1<<XTHAL_AMB_TRUSTED) 544 #define XTHAL_AM_PREFETCH (1<<XTHAL_AMB_PREFETCH) 545 #define XTHAL_AM_STREAM (1<<XTHAL_AMB_STREAM) 546 #endif /*0*/ 547 548 /* 549 * Allowed Access Modes (bit combinations). 550 * 551 * Columns are: 552 * "FOGIWACE" 553 * Access mode bits (see XTHAL_AMB_xxx above). 554 * <letter> = bit is set 555 * '-' = bit is clear 556 * '.' = bit is irrelevant / don't care, as follows: 557 * E=1 makes all others irrelevant 558 * W,F relevant only for stores 559 * "2345" 560 * Indicates which Xtensa releases support the corresponding 561 * access mode. Releases for each character column are: 562 * 2 = prior to T1020.2: T1015 (V1.5), T1020.0, T1020.1 563 * 3 = T1020.2 and later: T1020.2+, T1030 564 * 4 = T1040 565 * 5 = T1050 (maybe), LX1, LX2, LX2.1 566 * 7 = LX2.2 567 * 8 = LX3, LX4 568 * 9 = LX5 569 * And the character column contents are: 570 * <number> = supported by release(s) 571 * "." = unsupported by release(s) 572 * "?" = support unknown 573 */ 574 /* foMGIWACE 2345789 */ 575 /* For instruction fetch: */ 576 #define XTHAL_FAM_EXCEPTION 0x001 /* ........E 2345789 exception */ 577 /*efine XTHAL_FAM_ISOLATE*/ /*0x012*/ /* .---I.-C- ....... isolate */ 578 #define XTHAL_FAM_BYPASS 0x000 /* .----.--- 2345789 bypass */ 579 /*efine XTHAL_FAM_NACACHED*/ /*0x002*/ /* .----.-C- ....... cached no-allocate (frozen) */ 580 #define XTHAL_FAM_CACHED 0x006 /* .----.AC- 2345789 cached */ 581 /* For data load: */ 582 #define XTHAL_LAM_EXCEPTION 0x001 /* ........E 2345789 exception */ 583 #define XTHAL_LAM_ISOLATE 0x012 /* .---I.-C- 2345789 isolate */ 584 #define XTHAL_LAM_BYPASS 0x000 /* .O---.--- 2...... bypass speculative */ 585 #define XTHAL_LAM_BYPASSG 0x020 /* .O-G-.--- .345789 bypass guarded */ 586 #define XTHAL_LAM_CACHED_NOALLOC 0x002 /* .O---.-C- 2345789 cached no-allocate speculative */ 587 #define XTHAL_LAM_NACACHED XTHAL_LAM_CACHED_NOALLOC 588 #define XTHAL_LAM_NACACHEDG 0x022 /* .O-G-.-C- .?..... cached no-allocate guarded */ 589 #define XTHAL_LAM_CACHED 0x006 /* .----.AC- 2345789 cached speculative */ 590 #define XTHAL_LAM_COHCACHED 0x046 /* .-M--.AC- ....*89 cached speculative MP-coherent */ 591 /* For data store: */ 592 #define XTHAL_SAM_EXCEPTION 0x001 /* ........E 2345789 exception */ 593 #define XTHAL_SAM_ISOLATE 0x032 /* .--GI--C- 2345789 isolate */ 594 #define XTHAL_SAM_BYPASS 0x028 /* -O-G-W--- 2345789 bypass */ 595 #define XTHAL_SAM_WRITETHRU 0x02A /* -O-G-W-C- 2345789 writethrough */ 596 /*efine XTHAL_SAM_WRITETHRU_ALLOC*/ /*0x02E*/ /* -O-G-WAC- ....... writethrough allocate */ 597 #define XTHAL_SAM_WRITEBACK 0x026 /* F--G--AC- ...5789 writeback */ 598 #define XTHAL_SAM_WRITEBACK_NOALLOC 0x022 /* ?--G---C- .....89 writeback no-allocate */ 599 #define XTHAL_SAM_COHWRITEBACK 0x066 /* F-MG--AC- ....*89 writeback MP-coherent */ 600 /* For PIF attributes: */ /* -PIwrWCBUUUU ...9 */ 601 #define XTHAL_PAM_BYPASS 0x000 /* xxx00000xxxx ...9 bypass non-bufferable */ 602 #define XTHAL_PAM_BYPASS_BUF 0x010 /* xxx0000bxxxx ...9 bypass */ 603 #define XTHAL_PAM_CACHED_NOALLOC 0x030 /* xxx0001bxxxx ...9 cached no-allocate */ 604 #define XTHAL_PAM_WRITETHRU 0x0B0 /* xxx0101bxxxx ...9 writethrough (WT) */ 605 #define XTHAL_PAM_WRITEBACK_NOALLOC 0x0F0 /* xxx0111bxxxx ...9 writeback no-alloc (WBNA) */ 606 #define XTHAL_PAM_WRITEBACK 0x1F0 /* xxx1111bxxxx ...9 writeback (WB) */ 607 /*efine XTHAL_PAM_NORMAL*/ /*0x050*/ /* xxx0010bxxxx .... (unimplemented) */ 608 /*efine XTHAL_PAM_WRITETHRU_WA*/ /*0x130*/ /* xxx1001bxxxx .... (unimplemented, less likely) */ 609 /*efine XTHAL_PAM_WRITETHRU_RWA*/ /*0x1B0*/ /* xxx1101bxxxx .... (unimplemented, less likely) */ 610 /*efine XTHAL_PAM_WRITEBACK_WA*/ /*0x170*/ /* xxx1011bxxxx .... (unimplemented, less likely) */ 611 612 613 #if 0 614 /* 615 Cache attribute encoding for CACHEATTR (per ISA): 616 (Note: if this differs from ISA Ref Manual, ISA has precedence) 617 618 Inst-fetches Loads Stores 619 ------------- ------------ ------------- 620 0x0 FCA_EXCEPTION LCA_NACACHED SCA_WRITETHRU cached no-allocate (previously misnamed "uncached") 621 0x1 FCA_CACHED LCA_CACHED SCA_WRITETHRU cached 622 0x2 FCA_BYPASS LCA_BYPASS_G* SCA_BYPASS bypass cache (what most people call uncached) 623 0x3 FCA_CACHED LCA_CACHED SCA_WRITEALLOCF write-allocate 624 or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented) 625 0x4 FCA_CACHED LCA_CACHED SCA_WRITEBACK[M] write-back [MP-coherent] 626 or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented) 627 0x5 FCA_CACHED LCA_CACHED SCA_WRITEBACK_NOALLOC write-back no-allocate 628 or FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (if unimplemented) 629 0x6..D FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (reserved) 630 0xE FCA_EXCEPTION LCA_ISOLATE SCA_ISOLATE isolate 631 0xF FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION illegal 632 * Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G) 633 */ 634 #endif /*0*/ 635 636 637 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) 638 #ifdef __cplusplus 639 extern "C" { 640 #endif 641 642 643 /*---------------------------------------------------------------------- 644 Register Windows 645 ----------------------------------------------------------------------*/ 646 647 /* This spill any live register windows (other than the caller's): 648 * (NOTE: current implementation require privileged code, but 649 * a user-callable implementation is possible.) */ 650 extern void xthal_window_spill( void ); 651 652 653 /*---------------------------------------------------------------------- 654 Optional/Custom Processor State 655 ----------------------------------------------------------------------*/ 656 657 /* validate & invalidate the TIE register file */ 658 extern void xthal_validate_cp(int); 659 extern void xthal_invalidate_cp(int); 660 661 /* read and write cpenable register */ 662 extern void xthal_set_cpenable(unsigned); 663 extern unsigned xthal_get_cpenable(void); 664 665 666 /*---------------------------------------------------------------------- 667 Interrupts 668 ----------------------------------------------------------------------*/ 669 670 /* the number of interrupt levels */ 671 extern const unsigned char Xthal_num_intlevels; 672 /* the number of interrupts */ 673 extern const unsigned char Xthal_num_interrupts; 674 /* the highest level of interrupts masked by PS.EXCM */ 675 extern const unsigned char Xthal_excm_level; 676 677 /* mask for level of interrupts */ 678 extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS]; 679 /* mask for level 0 to N interrupts */ 680 extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS]; 681 682 /* level of each interrupt */ 683 extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS]; 684 685 /* type per interrupt */ 686 extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS]; 687 688 /* masks of each type of interrupt */ 689 extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES]; 690 691 /* interrupt numbers assigned to each timer interrupt */ 692 extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS]; 693 694 /* INTENABLE,INTERRUPT,INTSET,INTCLEAR register access functions: */ 695 extern unsigned xthal_get_intenable( void ); 696 extern void xthal_set_intenable( unsigned ); 697 extern unsigned xthal_get_interrupt( void ); 698 #define xthal_get_intread xthal_get_interrupt /* backward compatibility */ 699 700 /* These two functions are deprecated. Use the newer functions 701 xthal_interrupt_trigger and xthal_interrupt_clear instead. */ 702 extern void xthal_set_intset( unsigned ); 703 extern void xthal_set_intclear( unsigned ); 704 705 706 /*---------------------------------------------------------------------- 707 Debug 708 ----------------------------------------------------------------------*/ 709 710 /* Number of instruction and data break registers: */ 711 extern const int Xthal_num_ibreak; 712 extern const int Xthal_num_dbreak; 713 714 715 /*---------------------------------------------------------------------- 716 Core Counter 717 ----------------------------------------------------------------------*/ 718 719 /* counter info */ 720 extern const unsigned char Xthal_have_ccount; /* set if CCOUNT register present */ 721 extern const unsigned char Xthal_num_ccompare; /* number of CCOMPAREn registers */ 722 723 /* get CCOUNT register (if not present return 0) */ 724 extern unsigned xthal_get_ccount(void); 725 726 /* set and get CCOMPAREn registers (if not present, get returns 0) */ 727 extern void xthal_set_ccompare(int, unsigned); 728 extern unsigned xthal_get_ccompare(int); 729 730 731 /*---------------------------------------------------------------------- 732 Miscellaneous 733 ----------------------------------------------------------------------*/ 734 735 extern const unsigned char Xthal_have_prid; 736 extern const unsigned char Xthal_have_exceptions; 737 extern const unsigned char Xthal_xea_version; 738 extern const unsigned char Xthal_have_interrupts; 739 extern const unsigned char Xthal_have_highlevel_interrupts; 740 extern const unsigned char Xthal_have_nmi; 741 742 extern unsigned xthal_get_prid( void ); 743 744 745 /*---------------------------------------------------------------------- 746 Virtual interrupt prioritization (DEPRECATED) 747 ----------------------------------------------------------------------*/ 748 749 /* Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities: */ 750 extern unsigned xthal_vpri_to_intlevel(unsigned vpri); 751 extern unsigned xthal_intlevel_to_vpri(unsigned intlevel); 752 753 /* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */ 754 /* These functions are deprecated. Use xthal_interrupt_enable and xthal_interrupt_disable instead. */ 755 extern unsigned xthal_int_enable(unsigned); 756 extern unsigned xthal_int_disable(unsigned); 757 758 /* Set/get virtual priority of an interrupt: */ 759 extern int xthal_set_int_vpri(int intnum, int vpri); 760 extern int xthal_get_int_vpri(int intnum); 761 762 /* Set/get interrupt lockout level for exclusive access to virtual priority data structures: */ 763 extern void xthal_set_vpri_locklevel(unsigned intlevel); 764 extern unsigned xthal_get_vpri_locklevel(void); 765 766 /* Set/get current virtual interrupt priority: */ 767 extern unsigned xthal_set_vpri(unsigned vpri); 768 extern unsigned xthal_get_vpri(void); 769 extern unsigned xthal_set_vpri_intlevel(unsigned intlevel); 770 extern unsigned xthal_set_vpri_lock(void); 771 772 773 /*---------------------------------------------------------------------- 774 Generic Interrupt Trampolining Support (DEPRECATED) 775 ----------------------------------------------------------------------*/ 776 777 typedef void (XtHalVoidFunc)(void); 778 779 /* Bitmask of interrupts currently trampolining down: */ 780 extern unsigned Xthal_tram_pending; 781 782 /* 783 * Bitmask of which interrupts currently trampolining down synchronously are 784 * actually enabled; this bitmask is necessary because INTENABLE cannot hold 785 * that state (sync-trampolining interrupts must be kept disabled while 786 * trampolining); in the current implementation, any bit set here is not set 787 * in INTENABLE, and vice-versa; once a sync-trampoline is handled (at level 788 * one), its enable bit must be moved from here to INTENABLE: 789 */ 790 extern unsigned Xthal_tram_enabled; 791 792 /* Bitmask of interrupts configured for sync trampolining: */ 793 extern unsigned Xthal_tram_sync; 794 795 /* Trampoline support functions: */ 796 extern unsigned xthal_tram_pending_to_service( void ); 797 extern void xthal_tram_done( unsigned serviced_mask ); 798 extern int xthal_tram_set_sync( int intnum, int sync ); 799 extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn ); 800 801 802 /*---------------------------------------------------------------------- 803 Internal Memories 804 ----------------------------------------------------------------------*/ 805 806 extern const unsigned char Xthal_num_instrom; 807 extern const unsigned char Xthal_num_instram; 808 extern const unsigned char Xthal_num_datarom; 809 extern const unsigned char Xthal_num_dataram; 810 extern const unsigned char Xthal_num_xlmi; 811 812 /* Each of the following arrays contains at least one entry, 813 * or as many entries as needed if more than one: */ 814 extern const unsigned int Xthal_instrom_vaddr[]; 815 extern const unsigned int Xthal_instrom_paddr[]; 816 extern const unsigned int Xthal_instrom_size []; 817 extern const unsigned int Xthal_instram_vaddr[]; 818 extern const unsigned int Xthal_instram_paddr[]; 819 extern const unsigned int Xthal_instram_size []; 820 extern const unsigned int Xthal_datarom_vaddr[]; 821 extern const unsigned int Xthal_datarom_paddr[]; 822 extern const unsigned int Xthal_datarom_size []; 823 extern const unsigned int Xthal_dataram_vaddr[]; 824 extern const unsigned int Xthal_dataram_paddr[]; 825 extern const unsigned int Xthal_dataram_size []; 826 extern const unsigned int Xthal_xlmi_vaddr[]; 827 extern const unsigned int Xthal_xlmi_paddr[]; 828 extern const unsigned int Xthal_xlmi_size []; 829 830 831 /*---------------------------------------------------------------------- 832 Cache 833 ----------------------------------------------------------------------*/ 834 835 /* number of cache sets in log2(lines per way) */ 836 extern const unsigned char Xthal_icache_setwidth; 837 extern const unsigned char Xthal_dcache_setwidth; 838 /* cache set associativity (number of ways) */ 839 extern const unsigned int Xthal_icache_ways; 840 extern const unsigned int Xthal_dcache_ways; 841 /* cache features */ 842 extern const unsigned char Xthal_icache_line_lockable; 843 extern const unsigned char Xthal_dcache_line_lockable; 844 845 /* cache attribute register control (used by other HAL routines) */ 846 extern unsigned xthal_get_cacheattr( void ); 847 extern unsigned xthal_get_icacheattr( void ); 848 extern unsigned xthal_get_dcacheattr( void ); 849 extern void xthal_set_cacheattr( unsigned ); 850 extern void xthal_set_icacheattr( unsigned ); 851 extern void xthal_set_dcacheattr( unsigned ); 852 /* set cache attribute (access modes) for a range of memory */ 853 extern int xthal_set_region_attribute( void *addr, unsigned size, 854 unsigned cattr, unsigned flags ); 855 /* Bits of flags parameter to xthal_set_region_attribute(): */ 856 #define XTHAL_CAFLAG_EXPAND 0x000100 /* only expand allowed access to range, don't reduce it */ 857 #define XTHAL_CAFLAG_EXACT 0x000200 /* return error if can't apply change to exact range specified */ 858 #define XTHAL_CAFLAG_NO_PARTIAL 0x000400 /* don't apply change to regions partially covered by range */ 859 #define XTHAL_CAFLAG_NO_AUTO_WB 0x000800 /* don't writeback data after leaving writeback attribute */ 860 #define XTHAL_CAFLAG_NO_AUTO_INV 0x001000 /* don't invalidate after disabling cache (entering bypass) */ 861 862 /* enable caches */ 863 extern void xthal_icache_enable( void ); /* DEPRECATED */ 864 extern void xthal_dcache_enable( void ); /* DEPRECATED */ 865 /* disable caches */ 866 extern void xthal_icache_disable( void ); /* DEPRECATED */ 867 extern void xthal_dcache_disable( void ); /* DEPRECATED */ 868 869 /* whole cache operations (privileged) */ 870 extern void xthal_icache_all_invalidate( void ); 871 extern void xthal_dcache_all_invalidate( void ); 872 extern void xthal_dcache_all_writeback( void ); 873 extern void xthal_dcache_all_writeback_inv( void ); 874 extern void xthal_icache_all_unlock( void ); 875 extern void xthal_dcache_all_unlock( void ); 876 877 /* address-range cache operations (privileged) */ 878 /* prefetch and lock specified memory range into cache */ 879 extern void xthal_icache_region_lock( void *addr, unsigned size ); 880 extern void xthal_dcache_region_lock( void *addr, unsigned size ); 881 /* unlock from cache */ 882 extern void xthal_icache_region_unlock( void *addr, unsigned size ); 883 extern void xthal_dcache_region_unlock( void *addr, unsigned size ); 884 885 /* huge-range cache operations (privileged) (EXPERIMENTAL) */ 886 extern void xthal_icache_hugerange_invalidate( void *addr, unsigned size ); 887 extern void xthal_icache_hugerange_unlock( void *addr, unsigned size ); 888 extern void xthal_dcache_hugerange_invalidate( void *addr, unsigned size ); 889 extern void xthal_dcache_hugerange_unlock( void *addr, unsigned size ); 890 extern void xthal_dcache_hugerange_writeback( void *addr, unsigned size ); 891 extern void xthal_dcache_hugerange_writeback_inv( void *addr, unsigned size ); 892 893 # ifndef XTHAL_USE_CACHE_MACROS 894 /* cache line operations (privileged) */ 895 extern void xthal_icache_line_lock(void *addr); 896 extern void xthal_dcache_line_lock(void *addr); 897 extern void xthal_icache_line_unlock(void *addr); 898 extern void xthal_dcache_line_unlock(void *addr); 899 # endif 900 901 902 903 /*---------------------------------------------------------------------- 904 Local Memory ECC/Parity 905 ----------------------------------------------------------------------*/ 906 907 /* Inject memory errors; flags is bit combination of XTHAL_MEMEP_F_xxx: */ 908 extern void xthal_memep_inject_error(void *addr, int size, int flags); 909 910 911 912 /*---------------------------------------------------------------------- 913 Memory Management Unit 914 ----------------------------------------------------------------------*/ 915 916 extern const unsigned char Xthal_have_spanning_way; 917 extern const unsigned char Xthal_have_identity_map; 918 extern const unsigned char Xthal_have_mimic_cacheattr; 919 extern const unsigned char Xthal_have_xlt_cacheattr; 920 extern const unsigned char Xthal_have_cacheattr; 921 extern const unsigned char Xthal_have_tlbs; 922 923 extern const unsigned char Xthal_mmu_asid_bits; /* 0 .. 8 */ 924 extern const unsigned char Xthal_mmu_asid_kernel; 925 extern const unsigned char Xthal_mmu_rings; /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */ 926 extern const unsigned char Xthal_mmu_ring_bits; 927 extern const unsigned char Xthal_mmu_sr_bits; 928 extern const unsigned char Xthal_mmu_ca_bits; 929 extern const unsigned int Xthal_mmu_max_pte_page_size; 930 extern const unsigned int Xthal_mmu_min_pte_page_size; 931 932 extern const unsigned char Xthal_itlb_way_bits; 933 extern const unsigned char Xthal_itlb_ways; 934 extern const unsigned char Xthal_itlb_arf_ways; 935 extern const unsigned char Xthal_dtlb_way_bits; 936 extern const unsigned char Xthal_dtlb_ways; 937 extern const unsigned char Xthal_dtlb_arf_ways; 938 939 /* Return error codes for hal functions */ 940 941 /* function sucessful, operation completed as expected */ 942 #define XTHAL_SUCCESS 0 943 /* XTHAL_CAFLAGS_NO_PARTIAL was specified, and no full region is 944 * covered by the address range. */ 945 #define XTHAL_NO_REGIONS_COVERED -1 946 /* The XTHAL_CAFLAGS_EXACT flag was given, but no exact mapping is possible. */ 947 #define XTHAL_INEXACT -2 948 /* The supplied address doesn't correspond to the start of a region. */ 949 #define XTHAL_INVALID_ADDRESS -3 950 /* This functionality is not available on this architecture. */ 951 #define XTHAL_UNSUPPORTED -4 952 /* Translation failed because vaddr and paddr were not aligned. */ 953 #define XTHAL_ADDRESS_MISALIGNED -5 954 /* There is mapping for the supplied address. */ 955 #define XTHAL_NO_MAPPING -6 956 /* The requested access rights are not supported */ 957 #define XTHAL_BAD_ACCESS_RIGHTS -7 958 /* The requested memory type is not supported */ 959 #define XTHAL_BAD_MEMORY_TYPE -8 960 /* The entries supplied are not properly aligned to the MPU's background map. */ 961 #define XTHAL_MAP_NOT_ALIGNED -9 962 /* There are not enough MPU entries available to do the requeste mapping. */ 963 #define XTHAL_OUT_OF_ENTRIES -10 964 /* The entries supplied are not properly ordered for the MPU. */ 965 #define XTHAL_OUT_OF_ORDER_MAP -11 966 /* an invalid argument such as a null pointer was supplied to the function */ 967 #define XTHAL_INVALID -12 968 /* specified region is of zero size, therefore no mapping is done. */ 969 #define XTHAL_ZERO_SIZED_REGION -13 970 /* specified range wraps around '0' */ 971 #define XTHAL_INVALID_ADDRESS_RANGE -14 972 973 /* 974 For backward compatibility we retain the following inconsistenly named 975 constants. Do not use them as they may be removed in a future release. 976 */ 977 #define XCHAL_SUCCESS XTHAL_SUCCESS 978 #define XCHAL_ADDRESS_MISALIGNED XTHAL_ADDRESS_MISALIGNED 979 #define XCHAL_INEXACT XTHAL_INEXACT 980 #define XCHAL_INVALID_ADDRESS XTHAL_INVALID_ADDRESS 981 #define XCHAL_UNSUPPORTED_ON_THIS_ARCH XTHAL_UNSUPPORTED 982 #define XCHAL_NO_PAGES_MAPPED XTHAL_NO_REGIONS_COVERED 983 984 985 /* Convert between virtual and physical addresses (through static maps only) 986 * WARNING: these two functions may go away in a future release; 987 * don't depend on them! 988 */ 989 extern int xthal_static_v2p( unsigned vaddr, unsigned *paddrp ); 990 extern int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached ); 991 992 extern int xthal_set_region_translation(void* vaddr, void* paddr, 993 unsigned size, unsigned cache_atr, unsigned flags); 994 extern int xthal_v2p(void*, void**, unsigned*, unsigned*); 995 extern int xthal_invalidate_region(void* addr); 996 extern int xthal_set_region_translation_raw(void *vaddr, void *paddr, unsigned cattr); 997 998 /*------------------------------------------------------------------------ 999 MPU (Memory Protection Unit) 1000 -------------------------------------------------------------------------*/ 1001 1002 /* 1003 * General notes on MPU (Memory Protection Unit): 1004 * 1005 * The MPU supports setting the access rights (read, write, execute) as 1006 * well as the memory type (cacheablity, ...) 1007 * for regions of memory. The granularity can be as small as 32 bytes. 1008 * (XCHAL_MPU_ALIGN specifies the granularity for any specific MPU config) 1009 * 1010 * The MPU doesn't support mapping between virtual and physical addresses. 1011 * 1012 * The MPU contains a fixed number of map changeable forground map entries, 1013 * and a background map which is fixed at configuration time. 1014 * 1015 * Each entry has a start address (up to 27 bits), valid flag, 1016 * access rights (4 bits), and memory type (9 bits); 1017 * 1018 */ 1019 1020 1021 /* 1022 MPU access rights constants: 1023 Only the combinations listed below are supported by the MPU. 1024 */ 1025 1026 #define XTHAL_AR_NONE 0 /* no access */ 1027 #define XTHAL_AR_R 4 /* Kernel read, User no access*/ 1028 #define XTHAL_AR_RX 5 /* Kernel read/execute, User no access */ 1029 #define XTHAL_AR_RW 6 /* Kernel read/write, User no access */ 1030 #define XTHAL_AR_RWX 7 /* Kernel read/write/execute, User no access */ 1031 #define XTHAL_AR_Ww 8 /* Kernel write, User write */ 1032 #define XTHAL_AR_RWrwx 9 /* Kernel read/write , User read/write/execute */ 1033 #define XTHAL_AR_RWr 10 /* Kernel read/write, User read */ 1034 #define XTHAL_AR_RWXrx 11 /* Kernel read/write/execute, User read/execute */ 1035 #define XTHAL_AR_Rr 12 /* Kernel read, User read */ 1036 #define XTHAL_AR_RXrx 13 /* Kernel read/execute, User read/execute */ 1037 #define XTHAL_AR_RWrw 14 /* Kernel read/write, User read/write */ 1038 #define XTHAL_AR_RWXrwx 15 /* Kernel read/write/execute, 1039 User read/write/execute */ 1040 1041 #define XTHAL_AR_WIDTH 4 /* # bits used to encode access rights */ 1042 1043 /* If the bit XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS is set in the accessRights 1044 * argument to xthal_mpu_set_region_attribute(), or to the cattr argument of 1045 * xthal_set_region_attribute() then the existing access rights for the first 1046 * byte of the region will be used as the access rights of the new region. 1047 */ 1048 #define XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS 0x00002000 1049 1050 /* If the bit XTHAL_MPU_USE_EXISTING_MEMORY_TYPE is set in the memoryType 1051 * argument to xthal_mpu_set_region_attribute(), or to the cattr argument of 1052 * xthal_set_region_attribute() then the existing memory type for the first 1053 * byte of the region will be used as the memory type of the new region. 1054 */ 1055 #define XTHAL_MPU_USE_EXISTING_MEMORY_TYPE 0x00004000 1056 1057 /* The following groups of constants are bit-wise or'd together to specify 1058 * the memory type as input to the macros and functions that accept an 1059 * unencoded memory type specifier: 1060 * XTHAL_ENCODE_MEMORY_TYPE, xthal_encode_memory_type, 1061 * xthal_mpu_set_region_attribute(), and xthal_set_region_attribute(). 1062 * 1063 * example: 1064 * XTHAL_MEM_DEVICE | XTHAL_MEM_INTERRUPTIBLE | XTHAL_MEM_SYSTEM_SHARABLE 1065 * 1066 * or 1067 * XTHAL_MEM_WRITEBACK | XTHAL_MEM_INNER_SHAREABLE 1068 * 1069 * If it is desired to specify different attributes for the system and 1070 * local cache, then macro XTHAL_MEM_PROC_CACHE is used: 1071 * 1072 * XTHAL_MEM_PROC_CACHE(XTHAL_MEM_WRITEBACK, XTHAL_MEM_WRITETHRU) 1073 * 1074 * indicates the shared cache is writeback, but the processor's local cache 1075 * is writethrough. 1076 * 1077 */ 1078 1079 /* The following group of constants are used to specify cache attributes of 1080 * an MPU entry. If the processors local cache and the system's shared cache 1081 * have the same attributes (or if there aren't distinct local and shared 1082 * caches) then the constant can be used directly. If different attributes 1083 * for the shared and local caches, then use these constants as the parameters 1084 * to the XTHAL_MEM_PROC_CACHE() macro. 1085 */ 1086 #define XTHAL_MEM_DEVICE 0x00008000 1087 #define XTHAL_MEM_NON_CACHEABLE 0x00090000 1088 #define XTHAL_MEM_WRITETHRU_NOALLOC 0x00080000 1089 #define XTHAL_MEM_WRITETHRU 0x00040000 1090 #define XTHAL_MEM_WRITETHRU_WRITEALLOC 0x00060000 1091 #define XTHAL_MEM_WRITEBACK_NOALLOC 0x00050000 1092 #define XTHAL_MEM_WRITEBACK 0x00070000 1093 1094 /* Indicates a read is interruptible. Only applicable to devices */ 1095 #define XTHAL_MEM_INTERRUPTIBLE 0x08000000 1096 1097 /* Indicates if writes to this memory are bufferable ... only applicable 1098 * to devices, and non-cacheable memory. 1099 */ 1100 #define XTHAL_MEM_BUFFERABLE 0x01000000 1101 1102 /* The following group of constants indicates the scope of the sharing of 1103 * the memory region. XTHAL_MEM_INNER_SHAREABLE and XTHAL_MEM_OUTER_SHARABLE are 1104 * only applicable to cacheable regions. XTHAL_MEM_SYSTEM_SHAREABLE is only 1105 * applicable to devices and non-cacheable regions. 1106 */ 1107 #define XTHAL_MEM_NON_SHAREABLE 0x00000000 1108 #define XTHAL_MEM_INNER_SHAREABLE 0x02000000 1109 #define XTHAL_MEM_OUTER_SHAREABLE 0x04000000 1110 #define XTHAL_MEM_SYSTEM_SHAREABLE 0x06000000 1111 1112 1113 /* 1114 * This macro is needed when the cache attributes are different for the shared 1115 * and processor's local caches. For example: 1116 * 1117 * XTHAL_MEM_PROC_CACHE(XTHAL_MEM_WRITEBACK, XTHAL_MEM_NON_CACHEABLE) 1118 * creates a memory type that is writeback cacheable in the system cache, and not 1119 * cacheable in the processor's local cache. 1120 */ 1121 #define XTHAL_MEM_PROC_CACHE(system, processor) \ 1122 (((system) & 0x000f0000) | (((processor) & 0x000f0000 ) << 4) | \ 1123 (((system) & XTHAL_MEM_DEVICE) | ((processor) & XTHAL_MEM_DEVICE))) 1124 1125 /* 1126 * This macro converts a bit-wise combination of the XTHAL_MEM_... constants 1127 * to the corresponding MPU memory type (9-bits). 1128 * 1129 * Unsupported combinations are mapped to the best available substitute. 1130 * 1131 * The same functionality plus error checking is available from 1132 * xthal_encode_memory_type(). 1133 */ 1134 #define XTHAL_ENCODE_MEMORY_TYPE(x) \ 1135 (((x) & 0xffffe000) ? \ 1136 (_XTHAL_MEM_IS_DEVICE((x)) ? _XTHAL_ENCODE_DEVICE((x)) : \ 1137 (_XTHAL_IS_SYSTEM_NONCACHEABLE((x)) ? \ 1138 _XTHAL_ENCODE_SYSTEM_NONCACHEABLE((x)) : \ 1139 _XTHAL_ENCODE_SYSTEM_CACHEABLE((x)))) : (x)) 1140 1141 /* 1142 * This structure is used to represent each MPU entry (both foreground and 1143 * background). The internal representation of the structure is subject to 1144 * change, so it should only be accessed by the XTHAL_MPU_ENTRY_... macros 1145 * below. 1146 */ 1147 typedef struct xthal_MPU_entry 1148 { 1149 unsigned as; /* virtual start address, and valid bit */ 1150 unsigned at; /* access rights, and memory type (and space for entry index) */ 1151 } xthal_MPU_entry; 1152 1153 extern const xthal_MPU_entry Xthal_mpu_bgmap[]; 1154 1155 1156 1157 1158 /* 1159 * XTHAL_MPU_ENTRY creates an MPU entry from its component values. It is 1160 * intended for initializing an MPU map. Example: 1161 * const struct xthal_MPU_entry mpumap[] = 1162 { XTHAL_MPU_ENTRY( 0x00000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK), 1163 XTHAL_MPU_ENTRY( 0xE0000000, 1, XTHAL_AR_RWXrwx, 1164 XTHAL_MEM_NON_CACHEABLE | XTHAL_MEM_BUFFERABLE), 1165 XTHAL_MPU_ENTRY( 0xF0000000, 1, XTHAL_AR_RWX, 1166 XTHAL_MEM_NON_CACHEABLE | XTHAL_MEM_BUFFERABLE) }; 1167 xthal_write_map(mpumap, sizeof(mpumap) / sizeof(struct xthal_MPU_entry)); 1168 * 1169 */ 1170 #define XTHAL_MPU_ENTRY(vaddr, valid, access, memtype) \ 1171 { (((vaddr) & 0xffffffe0) | ((valid & 0x1))), \ 1172 (((XTHAL_ENCODE_MEMORY_TYPE(memtype)) << 12) | (((access) & 0xf) << 8)) } 1173 1174 /* 1175 * These macros get (or set) the specified field of the MPU entry. 1176 */ 1177 #define XTHAL_MPU_ENTRY_GET_VSTARTADDR(x) ((x).as & 0xffffffe0) 1178 1179 #define XTHAL_MPU_ENTRY_SET_VSTARTADDR(x, vaddr) (x).as = \ 1180 (((x).as) & 0x1) | ((vaddr) & 0xffffffe0) 1181 1182 #define XTHAL_MPU_ENTRY_GET_VALID(x) (((x).as & 0x1)) 1183 1184 #define XTHAL_MPU_ENTRY_SET_VALID(x, valid) (x).as = \ 1185 (((x).as & 0xfffffffe) | ((valid) & 0x1)) 1186 #define XTHAL_MPU_ENTRY_GET_ACCESS(x) ((((x).at) >> 8) & 0xf) 1187 1188 #define XTHAL_MPU_ENTRY_SET_ACCESS(x, accessRights) ((x).at = \ 1189 ((x).at & 0xfffff0ff) | (((accessRights) & 0xf) << 8)) 1190 1191 #define XTHAL_MPU_ENTRY_GET_MEMORY_TYPE(x) ((((x).at) >> 12) & 0x1ff) 1192 1193 #define XTHAL_MPU_ENTRY_SET_MEMORY_TYPE(x, memtype) ((x).at = \ 1194 ((x).at & 0xffe00fff) | (((XTHAL_ENCODE_MEMORY_TYPE(memtype)) & 0x1ff) << 12)) 1195 1196 /* 1197 * These functions accept encoded access rights, and return 1 if the 1198 * supplied memory type has the property specified by the function name, 1199 * otherwise they return 0. 1200 */ 1201 extern int xthal_is_kernel_readable(int accessRights); 1202 extern int xthal_is_kernel_writeable(int accessRights); 1203 extern int xthal_is_kernel_executable(int accessRights); 1204 extern int xthal_is_user_readable(int accessRights); 1205 extern int xthal_is_user_writeable (int accessRights); 1206 extern int xthal_is_user_executable(int accessRights); 1207 1208 1209 /* 1210 * This function converts a bit-wise combination of the XTHAL_MEM_.. constants 1211 * to the corresponding MPU memory type (9-bits). 1212 * 1213 * If none of the XTHAL_MEM_.. bits are present in the argument, then 1214 * bits 4-12 (9-bits) are returned ... this supports using an already encoded 1215 * memoryType (perhaps obtained from an xthal_MPU_entry structure) as input 1216 * to xthal_set_region_attribute(). 1217 * 1218 * This function first checks that the supplied constants are a valid and 1219 * supported combination. If not, it returns XTHAL_BAD_MEMORY_TYPE. 1220 */ 1221 extern int xthal_encode_memory_type(unsigned int x); 1222 1223 /* 1224 * This function accepts a 9-bit memory type value (such as returned by 1225 * XTHAL_MEM_ENTRY_GET_MEMORY_TYPE() or xthal_encode_memory_type(). They 1226 * return 1 if the memoryType has the property specified in the function 1227 * name and 0 otherwise. 1228 */ 1229 extern int xthal_is_cacheable(unsigned int memoryType); 1230 extern int xthal_is_writeback(unsigned int memoryType); 1231 extern int xthal_is_device(unsigned int memoryType); 1232 1233 /* 1234 * Copies the current MPU entry list into 'entries' which 1235 * must point to available memory of at least 1236 * sizeof(struct xthal_MPU_entry) * XCHAL_MPU_ENTRIES. 1237 * 1238 * This function returns XTHAL_SUCCESS. 1239 * XTHAL_INVALID, or 1240 * XTHAL_UNSUPPORTED. 1241 */ 1242 extern int xthal_read_map(struct xthal_MPU_entry* entries); 1243 1244 /* 1245 * Writes the map pointed to by 'entries' to the MPU. Before updating 1246 * the map, it commits any uncommitted 1247 * cache writes, and invalidates the cache if necessary. 1248 * 1249 * This function does not check for the correctness of the map. Generally 1250 * xthal_check_map() should be called first to check the map. 1251 * 1252 * If n == 0 then the existing map is cleared, and no new map is written 1253 * (useful for returning to reset state) 1254 * 1255 * If (n > 0 && n < XCHAL_MPU_ENTRIES) then a new map is written with 1256 * (XCHAL_MPU_ENTRIES-n) padding entries added to ensure a properly ordered 1257 * map. The resulting foreground map will be equivalent to the map vector 1258 * fg, but the position of the padding entries should not be relied upon. 1259 * 1260 * If n == XCHAL_MPU_ENTRIES then the complete map as specified by fg is 1261 * written. 1262 * 1263 * The CACHEADRDIS register will be set to enable caching any 512MB region 1264 * that is overlapped by an MPU region with a cacheable memory type. 1265 * Caching will be disabled if none of the 512 MB region is cacheable. 1266 * 1267 * xthal_write_map() disables the MPU foreground map during the MPU 1268 * update and relies on the background map. 1269 * 1270 * As a result any interrupt that does not meet the following conditions 1271 * must be disabled before calling xthal_write_map(): 1272 * 1) All code and data needed for the interrupt must be 1273 * mapped by the background map with sufficient access rights. 1274 * 2) The interrupt code must not access the MPU. 1275 * 1276 */ 1277 extern void xthal_write_map(const struct xthal_MPU_entry* entries, unsigned n); 1278 1279 /* 1280 * Checks if entry vector 'entries' of length 'n' is a valid MPU access map. 1281 * Returns: 1282 * XTHAL_SUCCESS if valid, 1283 * XTHAL_OUT_OF_ENTRIES 1284 * XTHAL_MAP_NOT_ALIGNED, 1285 * XTHAL_BAD_ACCESS_RIGHTS, 1286 * XTHAL_OUT_OF_ORDER_MAP, or 1287 * XTHAL_UNSUPPORTED if config doesn't have an MPU. 1288 */ 1289 extern int xthal_check_map(const struct xthal_MPU_entry* entries, unsigned n); 1290 1291 /* 1292 * Returns the MPU entry that maps 'vaddr'. If 'infgmap' is non-NULL then 1293 * *infgmap is set to 1 if 'vaddr' is mapped by the foreground map, and 1294 * *infgmap is set to 0 if 'vaddr' is mapped by the background map. 1295 */ 1296 extern struct xthal_MPU_entry xthal_get_entry_for_address(void* vaddr, 1297 int* infgmap); 1298 1299 /* 1300 * Scans the supplied MPU map and returns a value suitable for writing to 1301 * the CACHEADRDIS register: 1302 * Bits 0-7 -> 1 if there are no cacheable areas in the corresponding 512MB 1303 * region and 0 otherwise. 1304 * Bits 8-31 -> undefined. 1305 * This function can accept a partial memory map in the same manner 1306 * xthal_write_map() does, */ 1307 extern unsigned int 1308 xthal_calc_cacheadrdis(const struct xthal_MPU_entry* e, unsigned n); 1309 1310 /* 1311 * This function is intended as an MPU specific version of 1312 * xthal_set_region_attributes(). xthal_set_region_attributes() calls 1313 * this function for MPU configurations. 1314 * 1315 * This function sets the attributes for the region [vaddr, vaddr+size) 1316 * in the MPU. 1317 * 1318 * Depending on the state of the MPU this function will require from 1319 * 0 to 3 unused MPU entries. 1320 * 1321 * This function typically will move, add, and subtract entries from 1322 * the MPU map during execution, so that the resulting map may 1323 * be quite different than when the function was called. 1324 * 1325 * This function does make the following guarantees: 1326 * 1) The MPU access map remains in a valid state at all times 1327 * during its execution. 1328 * 2) At all points during (and after) completion the memoryType 1329 * and accessRights remain the same for all addresses 1330 * that are not in the range [vaddr, vaddr+size). 1331 * 3) If XTHAL_SUCCESS is returned, then the range 1332 * [vaddr, vaddr+size) will have the accessRights and memoryType 1333 * specified. 1334 * 4) The CACHEADRDIS register will be set to enable caching any 512MB region 1335 * that is overlapped by an MPU region with a cacheable memory type. 1336 * Caching will be disabled if none of the 512 MB region is cacheable. 1337 * 1338 * The accessRights parameter should be either a 4-bit value corresponding 1339 * to an MPU access mode (as defined by the XTHAL_AR_.. constants), or 1340 * XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS. 1341 * 1342 * The memoryType parameter should be either a bit-wise or-ing of XTHAL_MEM_.. 1343 * constants that represent a valid MPU memoryType, a 9-bit MPU memoryType 1344 * value, or XTHAL_MPU_USE_EXISTING_MEMORY_TYPE. 1345 * 1346 * In addition to the error codes that xthal_set_region_attribute() 1347 * returns, this function can also return: XTHAL_BAD_ACCESS_RIGHTS 1348 * (if the access rights bits map to an unsupported combination), or 1349 * XTHAL_OUT_OF_MAP_ENTRIES (if there are not enough unused MPU entries) 1350 * 1351 * If this function is called with an invalid MPU map, then this function 1352 * will return one of the codes that is returned by xthal_check_map(). 1353 * 1354 * The flag, XTHAL_CAFLAG_EXPAND, is not supported 1355 * 1356 */ 1357 1358 extern int xthal_mpu_set_region_attribute(void* vaddr, unsigned size, 1359 int accessRights, int memoryType, unsigned flags); 1360 1361 /* The following are internal implementation macros. These should not 1362 * be directly used except by the hal code and headers. 1363 */ 1364 1365 /* 1366 * Layout of the MPU specifier for: XTHAL_ENCODE_MEMORY_TYPE(), 1367 * xthal_encode_memory_type(), xthal_set_region_attribute(), 1368 * and xthal_mpu_set_region_attribute(). THIS IS SUBJECT TO CHANGE: 1369 * 1370 * Bits 0-3 - reserved for pass through of accessRights 1371 * Bits 4-12 - reserved for pass through of memoryType bits 1372 * Bit 13 - indicates to use existing access rights of region 1373 * Bit 14 - indicates to use existing memory type of region 1374 * Bit 15 - indicates device 1375 * Bit 16-19- system cache properties 1376 * Bit 20-23- local cache properties 1377 * Bit 24 - indicates bufferable 1378 * Bit 25-26- encodes shareability (1=inner, 2=outer, 3=system) 1379 * Bit 27 - indicates interruptible 1380 * Bits 28-31- reserved for future use 1381 */ 1382 #define _XTHAL_SYSTEM_CACHE_BITS 0x000f0000 1383 #define _XTHAL_LOCAL_CACHE_BITS 0x00f00000 1384 #define _XTHAL_MEM_SYSTEM_RWC_MASK 0x00070000 1385 #define _XTHAL_MEM_LOCAL_RWC_MASK 0x00700000 1386 #define _XTHAL_SHIFT_RWC 16 1387 1388 #define _XTHAL_MEM_ANY_SHAREABLE(x) (((x) & XTHAL_MEM_SYSTEM_SHAREABLE) ? 1 : 0) 1389 1390 #define _XTHAL_MEM_INNER_SHAREABLE(x) ((((x) & XTHAL_MEM_SYSTEM_SHAREABLE) \ 1391 == XTHAL_MEM_INNER_SHAREABLE) ? 1 : 0) 1392 1393 #define _XTHAL_MEM_IS_BUFFERABLE(x) (((x) & XTHAL_MEM_BUFFERABLE) ? 1 : 0) 1394 1395 #define _XTHAL_MEM_IS_DEVICE(x) (((x) & XTHAL_MEM_DEVICE) ? 1 : 0) 1396 1397 #define _XTHAL_NON_CACHEABLE_DOMAIN(x) \ 1398 (_XTHAL_MEM_IS_DEVICE(x) || _XTHAL_MEM_ANY_SHAREABLE(x)? 0x3 : 0) 1399 1400 #define _XTHAL_CACHEABLE_DOMAIN(x) (_XTHAL_MEM_ANY_SHAREABLE(x) ? \ 1401 0x3 : 0x1) 1402 1403 #define _XTHAL_MEM_CACHE_MASK(x) ((x) & _XTHAL_SYSTEM_CACHE_BITS) 1404 1405 #define _XTHAL_IS_SYSTEM_NONCACHEABLE(x) \ 1406 (((_XTHAL_MEM_CACHE_MASK(x) & XTHAL_MEM_NON_CACHEABLE) == \ 1407 XTHAL_MEM_NON_CACHEABLE) ? 1 : 0) 1408 1409 #define _XTHAL_ENCODE_DEVICE(x) \ 1410 (((((x) & XTHAL_MEM_INTERRUPTIBLE) ? 1 : 0) << 3) | \ 1411 (_XTHAL_NON_CACHEABLE_DOMAIN(x) << 1) | _XTHAL_MEM_IS_BUFFERABLE(x)) 1412 1413 #define _XTHAL_ENCODE_SYSTEM_NONCACHEABLE(x) \ 1414 (0x18 | (_XTHAL_NON_CACHEABLE_DOMAIN(x) << 1) \ 1415 | _XTHAL_MEM_IS_BUFFERABLE(x)) 1416 1417 #define _XTHAL_ENCODE_SYSTEM_CACHEABLE(x) \ 1418 (((((((x) & _XTHAL_LOCAL_CACHE_BITS) >> 4) & XTHAL_MEM_NON_CACHEABLE) == \ 1419 XTHAL_MEM_NON_CACHEABLE) ? 1 : 0) ? \ 1420 (_XTHAL_CACHEABLE_DOMAIN(x) << 4) : \ 1421 _XTHAL_ENCODE_SYSTEM_CACHEABLE_LOCAL_CACHEABLE(x)) | \ 1422 ((_XTHAL_MEM_INNER_SHAREABLE(x) << 3) | \ 1423 (_XTHAL_MEM_CACHE_MASK(x) & _XTHAL_MEM_SYSTEM_RWC_MASK) \ 1424 >> _XTHAL_SHIFT_RWC) 1425 1426 #define _XTHAL_ENCODE_SYSTEM_CACHEABLE_LOCAL_CACHEABLE(x) \ 1427 ((_XTHAL_CACHEABLE_DOMAIN(x) << 7) | (((((x) & _XTHAL_LOCAL_CACHE_BITS) ? \ 1428 ((x) & _XTHAL_LOCAL_CACHE_BITS) : \ 1429 (_XTHAL_MEM_CACHE_MASK(x) << 4)) \ 1430 & (_XTHAL_MEM_LOCAL_RWC_MASK)) >> _XTHAL_SHIFT_RWC )) 1431 1432 /* End of internal macros */ 1433 1434 /* The functions and constants below here have been deprecated.*/ 1435 #define XTHAL_MEM_NON_CACHED XTHAL_MEM_NON_CACHEABLE 1436 #define XTHAL_MEM_NON_SHARED XTHAL_MEM_NON_SHAREABLE 1437 #define XTHAL_MEM_INNER_SHARED XTHAL_MEM_INNER_SHAREABLE 1438 #define XTHAL_MEM_OUTER_SHARED XTHAL_MEM_OUTER_SHAREABLE 1439 #define XTHAL_MEM_SYSTEM_SHARED XTHAL_MEM_SYSTEM_SHAREABLE 1440 #define XTHAL_MEM_SW_SHAREABLE 0 1441 1442 #define xthal_is_cached(memoryType) (xthal_is_cacheable((memoryType))) 1443 extern int xthal_read_background_map(struct xthal_MPU_entry* entries); 1444 1445 /* end deprecated functions and constants */ 1446 1447 #ifdef __cplusplus 1448 } 1449 #endif 1450 #endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ 1451 1452 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 1453 1454 1455 1456 1457 /**************************************************************************** 1458 EXPERIMENTAL and DEPRECATED Definitions 1459 ****************************************************************************/ 1460 1461 1462 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) 1463 #ifdef __cplusplus 1464 extern "C" { 1465 #endif 1466 1467 #ifdef INCLUDE_DEPRECATED_HAL_CODE 1468 extern const unsigned char Xthal_have_old_exc_arch; 1469 extern const unsigned char Xthal_have_mmu; 1470 extern const unsigned int Xthal_num_regs; 1471 extern const unsigned char Xthal_num_iroms; 1472 extern const unsigned char Xthal_num_irams; 1473 extern const unsigned char Xthal_num_droms; 1474 extern const unsigned char Xthal_num_drams; 1475 extern const unsigned int Xthal_configid0; 1476 extern const unsigned int Xthal_configid1; 1477 #endif 1478 1479 #ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE 1480 #define XTHAL_24_BIT_BREAK 0x80000000 1481 #define XTHAL_16_BIT_BREAK 0x40000000 1482 extern const unsigned short Xthal_ill_inst_16[16]; 1483 #define XTHAL_DEST_REG 0xf0000000 /* Mask for destination register */ 1484 #define XTHAL_DEST_REG_INST 0x08000000 /* Branch address is in register */ 1485 #define XTHAL_DEST_REL_INST 0x04000000 /* Branch address is relative */ 1486 #define XTHAL_RFW_INST 0x00000800 1487 #define XTHAL_RFUE_INST 0x00000400 1488 #define XTHAL_RFI_INST 0x00000200 1489 #define XTHAL_RFE_INST 0x00000100 1490 #define XTHAL_RET_INST 0x00000080 1491 #define XTHAL_BREAK_INST 0x00000040 1492 #define XTHAL_SYSCALL_INST 0x00000020 1493 #define XTHAL_LOOP_END 0x00000010 /* Not set by xthal_inst_type */ 1494 #define XTHAL_JUMP_INST 0x00000008 /* Call or jump instruction */ 1495 #define XTHAL_BRANCH_INST 0x00000004 /* Branch instruction */ 1496 #define XTHAL_24_BIT_INST 0x00000002 1497 #define XTHAL_16_BIT_INST 0x00000001 1498 typedef struct xthal_state { 1499 unsigned pc; 1500 unsigned ar[16]; 1501 unsigned lbeg; 1502 unsigned lend; 1503 unsigned lcount; 1504 unsigned extra_ptr; 1505 unsigned cpregs_ptr[XTHAL_MAX_CPS]; 1506 } XTHAL_STATE; 1507 extern unsigned int xthal_inst_type(void *addr); 1508 extern unsigned int xthal_branch_addr(void *addr); 1509 extern unsigned int xthal_get_npc(XTHAL_STATE *user_state); 1510 #endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */ 1511 1512 #ifdef __cplusplus 1513 } 1514 #endif 1515 #endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ 1516 1517 #endif /*XTENSA_HAL_H*/ 1518 1519
