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Searched refs:XCHAL_CP0_SA_SIZE (Results 1 – 10 of 10) sorted by relevance

/hal_xtensa-2.7.6/include/xtensa/
Dxtruntime-core-state.h177 #if XCHAL_CP0_SA_SIZE > 0
178 STRUCT_AFIELD_A(char,1,XCHAL_CP0_SA_ALIGN,CS_SA_,cp0,XCHAL_CP0_SA_SIZE)
Dxtruntime-frames.h120 STRUCT_AFIELD (long,4,UEXC_,cp0, XCHAL_CP0_SA_SIZE / 4)
126 #define ALIGNPAD ((2 + XCHAL_HAVE_MAC16*2 + ((XCHAL_CP0_SA_SIZE%16)/4) + ((XCHAL_CP1_SA_SIZE%16)/4…
/hal_xtensa-2.7.6/zephyr/soc/intel_apl_adsp/xtensa/config/
Dtie.h50 #define XCHAL_CP0_SA_SIZE 0 macro
/hal_xtensa-2.7.6/src/hal/
Dstate.c40 XCHAL_CP0_SA_SIZE,
/hal_xtensa-2.7.6/zephyr/soc/nxp_imx8/xtensa/config/
Dtie.h48 #define XCHAL_CP0_SA_SIZE 0 macro
/hal_xtensa-2.7.6/zephyr/soc/intel_cavs_18/xtensa/config/
Dtie.h45 #define XCHAL_CP0_SA_SIZE 72 /* size of state save area */ macro
/hal_xtensa-2.7.6/zephyr/soc/intel_s1000/xtensa/config/
Dtie.h46 #define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
/hal_xtensa-2.7.6/zephyr/soc/intel_cavs_25/xtensa/config/
Dtie.h45 #define XCHAL_CP0_SA_SIZE 72 /* size of state save area */ macro
/hal_xtensa-2.7.6/zephyr/soc/intel_cavs_20/xtensa/config/
Dtie.h45 #define XCHAL_CP0_SA_SIZE 72 /* size of state save area */ macro
/hal_xtensa-2.7.6/include/xtensa/config/
Dcore.h1088 # if XCHAL_CP0_SA_SIZE == 0
1136 # if XCHAL_CP0_SA_SIZE
1197 # if XCHAL_CP0_SA_SIZE
1296 #define XCHAL_CP0_SA_SIZE 0 macro