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Searched refs:ui32Base (Results 1 – 25 of 59) sorted by relevance

123

/hal_ti-latest/simplelink/source/ti/devices/cc32xx/driverlib/
Di2c.c86 _I2CBaseValid(uint32_t ui32Base) in _I2CBaseValid() argument
88 return((ui32Base == I2CA0_BASE)); in _I2CBaseValid()
106 _I2CIntNumberGet(uint32_t ui32Base) in _I2CIntNumberGet() argument
114 ASSERT(_I2CBaseValid(ui32Base)); in _I2CIntNumberGet()
128 if(ppui32I2CIntMap[i8Idx][0] == ui32Base) in _I2CIntNumberGet()
168 I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, in I2CMasterInitExpClk() argument
177 ASSERT(_I2CBaseValid(ui32Base)); in I2CMasterInitExpClk()
182 I2CMasterEnable(ui32Base); in I2CMasterInitExpClk()
204 HWREG(ui32Base + I2C_O_MTPR) = ui32TPR; in I2CMasterInitExpClk()
210 if(HWREG(ui32Base + I2C_O_PP) & I2C_PP_HS) in I2CMasterInitExpClk()
[all …]
Dshamd5.c72 SHAMD5DMAEnable(uint32_t ui32Base) in SHAMD5DMAEnable() argument
77 ASSERT(ui32Base == SHAMD5_BASE); in SHAMD5DMAEnable()
82 HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= in SHAMD5DMAEnable()
98 SHAMD5DMADisable(uint32_t ui32Base) in SHAMD5DMADisable() argument
103 ASSERT(ui32Base == SHAMD5_BASE); in SHAMD5DMADisable()
108 HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= in SHAMD5DMADisable()
133 SHAMD5IntStatus(uint32_t ui32Base, bool bMasked) in SHAMD5IntStatus() argument
141 ASSERT(ui32Base == SHAMD5_BASE); in SHAMD5IntStatus()
149 ui32IrqEnable = HWREG(ui32Base + SHAMD5_O_IRQENABLE); in SHAMD5IntStatus()
150 return((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & in SHAMD5IntStatus()
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Daes.c145 AESConfigSet(uint32_t ui32Base, uint32_t ui32Config) in AESConfigSet() argument
150 ASSERT(ui32Base == AES_BASE); in AESConfigSet()
196 if(HWREG(ui32Base + AES_O_CTRL) & AES_CTRL_SAVE_CONTEXT) in AESConfigSet()
204 HWREG(ui32Base + AES_O_CTRL) = ui32Config; in AESConfigSet()
226 AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key, uint32_t ui32Keysize) in AESKey1Set() argument
231 ASSERT(ui32Base == AES_BASE); in AESKey1Set()
239 HWREG(ui32Base + AES_O_KEY1_0) = * ((uint32_t *)(pui8Key + 0)); in AESKey1Set()
240 HWREG(ui32Base + AES_O_KEY1_1) = * ((uint32_t *)(pui8Key + 4)); in AESKey1Set()
241 HWREG(ui32Base + AES_O_KEY1_2) = * ((uint32_t *)(pui8Key + 8)); in AESKey1Set()
242 HWREG(ui32Base + AES_O_KEY1_3) = * ((uint32_t *)(pui8Key + 12)); in AESKey1Set()
[all …]
Di2c.h285 extern void I2CIntRegister(uint32_t ui32Base, void(pfnHandler)(void));
286 extern void I2CIntUnregister(uint32_t ui32Base);
287 extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
288 extern void I2CTxFIFOFlush(uint32_t ui32Base);
289 extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
290 extern void I2CRxFIFOFlush(uint32_t ui32Base);
291 extern uint32_t I2CFIFOStatus(uint32_t ui32Base);
292 extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data);
293 extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base,
295 extern uint32_t I2CFIFODataGet(uint32_t ui32Base);
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Ddes.c95 DESConfigSet(uint32_t ui32Base, uint32_t ui32Config) in DESConfigSet() argument
100 ASSERT(ui32Base == DES_BASE); in DESConfigSet()
105 ui32Config |= (HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT); in DESConfigSet()
110 HWREG(ui32Base + DES_O_CTRL) = ui32Config; in DESConfigSet()
129 DESKeySet(uint32_t ui32Base, uint8_t *pui8Key) in DESKeySet() argument
134 ASSERT(ui32Base == DES_BASE); in DESKeySet()
139 HWREG(ui32Base + DES_O_KEY1_L) = * ((uint32_t *)(pui8Key + 0)); in DESKeySet()
140 HWREG(ui32Base + DES_O_KEY1_H) = * ((uint32_t *)(pui8Key + 4)); in DESKeySet()
146 if(HWREG(ui32Base + DES_O_CTRL) & DES_CFG_TRIPLE) in DESKeySet()
148 HWREG(ui32Base + DES_O_KEY2_L) = * ((uint32_t *)(pui8Key + 8)); in DESKeySet()
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Dshamd5.h97 extern void SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32CryptoMode, uint8_t algConstFlag, uint8…
99 extern bool SHAMD5DataProcess(uint32_t ui32Base, uint8_t *pui8DataSrc,
101 extern void SHAMD5DataWrite(uint32_t ui32Base, uint8_t *pui8Src);
102 extern bool SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src);
103 extern void SHAMD5DMADisable(uint32_t ui32Base);
104 extern void SHAMD5DMAEnable(uint32_t ui32Base);
105 extern void SHAMD5DataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
106 extern void SHAMD5HMACKeySet(uint32_t ui32Base, uint8_t *pui8Src);
107 extern void SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint8_t *pui8Key,
109 extern void SHAMD5HMACPPKeySet(uint32_t ui32Base, uint8_t *pui8Src);
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/hal_ti-latest/simplelink/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/
Di2c.h168 I2CBaseValid(uint32_t ui32Base) in I2CBaseValid() argument
170 return(ui32Base == I2C0_BASE); in I2CBaseValid()
194 extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
222 I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd) in I2CMasterControl() argument
225 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterControl()
238 HWREG(ui32Base + I2C_O_MCTRL) = ui32Cmd; in I2CMasterControl()
265 I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, in I2CMasterSlaveAddrSet() argument
269 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterSlaveAddrSet()
273 HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive; in I2CMasterSlaveAddrSet()
288 I2CMasterEnable(uint32_t ui32Base) in I2CMasterEnable() argument
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Duart.h208 UARTBaseValid(uint32_t ui32Base) in UARTBaseValid() argument
210 return(( ui32Base == UART0_BASE ) || ( ui32Base == UART0_NONBUF_BASE ) || in UARTBaseValid()
211 ( ui32Base == UART1_BASE ) || ( ui32Base == UART1_NONBUF_BASE ) ); in UARTBaseValid()
236 UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) in UARTParityModeSet() argument
239 ASSERT(UARTBaseValid(ui32Base)); in UARTParityModeSet()
247 HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & in UARTParityModeSet()
270 UARTParityModeGet(uint32_t ui32Base) in UARTParityModeGet() argument
273 ASSERT(UARTBaseValid(ui32Base)); in UARTParityModeGet()
276 return(HWREG(ui32Base + UART_O_LCRH) & in UARTParityModeGet()
305 UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, in UARTFIFOLevelSet() argument
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Dtimer.h209 TimerBaseValid(uint32_t ui32Base) in TimerBaseValid() argument
211 return((ui32Base == GPT0_BASE) || (ui32Base == GPT1_BASE) || in TimerBaseValid()
212 (ui32Base == GPT2_BASE) || (ui32Base == GPT3_BASE)); in TimerBaseValid()
233 TimerEnable(uint32_t ui32Base, uint32_t ui32Timer) in TimerEnable() argument
236 ASSERT(TimerBaseValid(ui32Base)); in TimerEnable()
241 HWREG(ui32Base + GPT_O_CTL) |= ui32Timer & (GPT_CTL_TAEN | GPT_CTL_TBEN); in TimerEnable()
260 TimerDisable(uint32_t ui32Base, uint32_t ui32Timer) in TimerDisable() argument
263 ASSERT(TimerBaseValid(ui32Base)); in TimerDisable()
268 HWREG(ui32Base + GPT_O_CTL) &= ~(ui32Timer & in TimerDisable()
324 extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config);
[all …]
Duart.c74 UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, in UARTFIFOLevelGet() argument
80 ASSERT(UARTBaseValid(ui32Base)); in UARTFIFOLevelGet()
83 ui32Temp = HWREG(ui32Base + UART_O_IFLS); in UARTFIFOLevelGet()
96 UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, in UARTConfigSetExpClk() argument
102 ASSERT(UARTBaseValid(ui32Base)); in UARTConfigSetExpClk()
106 UARTDisable(ui32Base); in UARTConfigSetExpClk()
112 HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; in UARTConfigSetExpClk()
113 HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; in UARTConfigSetExpClk()
116 HWREG(ui32Base + UART_O_LCRH) = ui32Config; in UARTConfigSetExpClk()
125 UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, in UARTConfigGetExpClk() argument
[all …]
Dssi.h160 SSIBaseValid(uint32_t ui32Base) in SSIBaseValid() argument
162 return(ui32Base == SSI0_BASE || ui32Base == SSI1_BASE); in SSIBaseValid()
223 extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk,
240 SSIEnable(uint32_t ui32Base) in SSIEnable() argument
243 ASSERT(SSIBaseValid(ui32Base)); in SSIEnable()
246 HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_SSE; in SSIEnable()
261 SSIDisable(uint32_t ui32Base) in SSIDisable() argument
264 ASSERT(SSIBaseValid(ui32Base)); in SSIDisable()
267 HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_SSE); in SSIDisable()
288 extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data);
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Dudma.h343 uDMABaseValid(uint32_t ui32Base) in uDMABaseValid() argument
345 return(ui32Base == UDMA0_BASE); in uDMABaseValid()
362 uDMAEnable(uint32_t ui32Base) in uDMAEnable() argument
365 ASSERT(uDMABaseValid(ui32Base)); in uDMAEnable()
368 HWREG(ui32Base + UDMA_O_CFG) = UDMA_CFG_MASTERENABLE; in uDMAEnable()
384 uDMADisable(uint32_t ui32Base) in uDMADisable() argument
387 ASSERT(uDMABaseValid(ui32Base)); in uDMADisable()
390 HWREG(ui32Base + UDMA_O_CFG) = 0; in uDMADisable()
407 uDMAErrorStatusGet(uint32_t ui32Base) in uDMAErrorStatusGet() argument
410 ASSERT(uDMABaseValid(ui32Base)); in uDMAErrorStatusGet()
[all …]
Dadi.h108 ADIBaseValid(uint32_t ui32Base) in ADIBaseValid() argument
110 return(ui32Base == ADI2_BASE || ui32Base == ADI3_BASE || in ADIBaseValid()
111 ui32Base == AUX_ADI4_BASE); in ADIBaseValid()
147 ADI8RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) in ADI8RegWrite() argument
150 ASSERT(ADIBaseValid(ui32Base)); in ADI8RegWrite()
154 HWREGB(ui32Base + ui32Reg) = ui8Val; in ADI8RegWrite()
188 ADI16RegWrite(uint32_t ui32Base, uint32_t ui32Reg, in ADI16RegWrite() argument
192 ASSERT(ADIBaseValid(ui32Base)); in ADI16RegWrite()
196 HWREGH(ui32Base + (ui32Reg & 0xFE)) = ui16Val; in ADI16RegWrite()
230 ADI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) in ADI32RegWrite() argument
[all …]
Di2s.h271 I2SBaseValid(uint32_t ui32Base) in I2SBaseValid() argument
273 return(ui32Base == I2S0_BASE); in I2SBaseValid()
297 extern void I2SEnable(uint32_t ui32Base);
322 I2SDisable(uint32_t ui32Base) in I2SDisable() argument
325 ASSERT(I2SBaseValid(ui32Base)); in I2SDisable()
374 extern void I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg,
421 extern void I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg,
453 I2SClockConfigure(uint32_t ui32Base, uint32_t ui32ClkConfig) in I2SClockConfigure() argument
456 ASSERT(I2SBaseValid(ui32Base)); in I2SClockConfigure()
488 extern void I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase,
[all …]
Dtimer.c77 TimerIntNumberGet(uint32_t ui32Base) in TimerIntNumberGet() argument
83 switch(ui32Base) in TimerIntNumberGet()
111 TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) in TimerConfigure() argument
114 ASSERT(TimerBaseValid(ui32Base)); in TimerConfigure()
141 HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN); in TimerConfigure()
144 HWREG(ui32Base + GPT_O_CFG) = ui32Config >> 24; in TimerConfigure()
148 HWREG(ui32Base + GPT_O_TAMR) = (ui32Config & 0xFF) | GPT_TAMR_TAPWMIE; in TimerConfigure()
149 HWREG(ui32Base + GPT_O_TBMR) = in TimerConfigure()
159 TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) in TimerLevelControl() argument
162 ASSERT(TimerBaseValid(ui32Base)); in TimerLevelControl()
[all …]
Dssi.c68 SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, in SSIConfigSetExpClk() argument
79 ASSERT(SSIBaseValid(ui32Base)); in SSIConfigSetExpClk()
97 HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; in SSIConfigSetExpClk()
108 HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv; in SSIConfigSetExpClk()
114 HWREG(ui32Base + SSI_O_CR0) = ui32RegVal; in SSIConfigSetExpClk()
123 SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data) in SSIDataPutNonBlocking() argument
126 ASSERT(SSIBaseValid(ui32Base)); in SSIDataPutNonBlocking()
127 ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & in SSIDataPutNonBlocking()
131 if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) in SSIDataPutNonBlocking()
133 HWREG(ui32Base + SSI_O_DR) = ui32Data; in SSIDataPutNonBlocking()
[all …]
/hal_ti-latest/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/
Duart.h210 UARTBaseValid(uint32_t ui32Base) in UARTBaseValid() argument
212 return(( ui32Base == UART0_BASE ) || ( ui32Base == UART0_NONBUF_BASE ) || in UARTBaseValid()
213 ( ui32Base == UART1_BASE ) || ( ui32Base == UART1_NONBUF_BASE ) ); in UARTBaseValid()
238 UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) in UARTParityModeSet() argument
241 ASSERT(UARTBaseValid(ui32Base)); in UARTParityModeSet()
249 HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & in UARTParityModeSet()
272 UARTParityModeGet(uint32_t ui32Base) in UARTParityModeGet() argument
275 ASSERT(UARTBaseValid(ui32Base)); in UARTParityModeGet()
278 return(HWREG(ui32Base + UART_O_LCRH) & in UARTParityModeGet()
307 UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, in UARTFIFOLevelSet() argument
[all …]
Dtimer.h211 TimerBaseValid(uint32_t ui32Base) in TimerBaseValid() argument
213 return((ui32Base == GPT0_BASE) || (ui32Base == GPT1_BASE) || in TimerBaseValid()
214 (ui32Base == GPT2_BASE) || (ui32Base == GPT3_BASE)); in TimerBaseValid()
235 TimerEnable(uint32_t ui32Base, uint32_t ui32Timer) in TimerEnable() argument
238 ASSERT(TimerBaseValid(ui32Base)); in TimerEnable()
243 HWREG(ui32Base + GPT_O_CTL) |= ui32Timer & (GPT_CTL_TAEN | GPT_CTL_TBEN); in TimerEnable()
262 TimerDisable(uint32_t ui32Base, uint32_t ui32Timer) in TimerDisable() argument
265 ASSERT(TimerBaseValid(ui32Base)); in TimerDisable()
270 HWREG(ui32Base + GPT_O_CTL) &= ~(ui32Timer & in TimerDisable()
326 extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config);
[all …]
Duart.c76 UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, in UARTFIFOLevelGet() argument
82 ASSERT(UARTBaseValid(ui32Base)); in UARTFIFOLevelGet()
85 ui32Temp = HWREG(ui32Base + UART_O_IFLS); in UARTFIFOLevelGet()
98 UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, in UARTConfigSetExpClk() argument
104 ASSERT(UARTBaseValid(ui32Base)); in UARTConfigSetExpClk()
108 UARTDisable(ui32Base); in UARTConfigSetExpClk()
114 HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; in UARTConfigSetExpClk()
115 HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; in UARTConfigSetExpClk()
118 HWREG(ui32Base + UART_O_LCRH) = ui32Config; in UARTConfigSetExpClk()
127 UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, in UARTConfigGetExpClk() argument
[all …]
Dssi.h162 SSIBaseValid(uint32_t ui32Base) in SSIBaseValid() argument
164 return(ui32Base == SSI0_BASE || ui32Base == SSI1_BASE); in SSIBaseValid()
225 extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk,
242 SSIEnable(uint32_t ui32Base) in SSIEnable() argument
245 ASSERT(SSIBaseValid(ui32Base)); in SSIEnable()
248 HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_SSE; in SSIEnable()
263 SSIDisable(uint32_t ui32Base) in SSIDisable() argument
266 ASSERT(SSIBaseValid(ui32Base)); in SSIDisable()
269 HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_SSE); in SSIDisable()
290 extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data);
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Dudma.h345 uDMABaseValid(uint32_t ui32Base) in uDMABaseValid() argument
347 return(ui32Base == UDMA0_BASE); in uDMABaseValid()
364 uDMAEnable(uint32_t ui32Base) in uDMAEnable() argument
367 ASSERT(uDMABaseValid(ui32Base)); in uDMAEnable()
370 HWREG(ui32Base + UDMA_O_CFG) = UDMA_CFG_MASTERENABLE; in uDMAEnable()
386 uDMADisable(uint32_t ui32Base) in uDMADisable() argument
389 ASSERT(uDMABaseValid(ui32Base)); in uDMADisable()
392 HWREG(ui32Base + UDMA_O_CFG) = 0; in uDMADisable()
409 uDMAErrorStatusGet(uint32_t ui32Base) in uDMAErrorStatusGet() argument
412 ASSERT(uDMABaseValid(ui32Base)); in uDMAErrorStatusGet()
[all …]
Dadi.h110 ADIBaseValid(uint32_t ui32Base) in ADIBaseValid() argument
112 return(ui32Base == ADI2_BASE || ui32Base == ADI3_BASE || in ADIBaseValid()
113 ui32Base == AUX_ADI4_BASE); in ADIBaseValid()
149 ADI8RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) in ADI8RegWrite() argument
152 ASSERT(ADIBaseValid(ui32Base)); in ADI8RegWrite()
156 HWREGB(ui32Base + ui32Reg) = ui8Val; in ADI8RegWrite()
190 ADI16RegWrite(uint32_t ui32Base, uint32_t ui32Reg, in ADI16RegWrite() argument
194 ASSERT(ADIBaseValid(ui32Base)); in ADI16RegWrite()
198 HWREGH(ui32Base + (ui32Reg & 0xFE)) = ui16Val; in ADI16RegWrite()
232 ADI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) in ADI32RegWrite() argument
[all …]
Di2c.h170 I2CBaseValid(uint32_t ui32Base) in I2CBaseValid() argument
172 return(ui32Base == I2C0_BASE); in I2CBaseValid()
196 extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
224 I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd) in I2CMasterControl() argument
227 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterControl()
267 I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, in I2CMasterSlaveAddrSet() argument
271 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterSlaveAddrSet()
290 I2CMasterEnable(uint32_t ui32Base) in I2CMasterEnable() argument
293 ASSERT(I2CBaseValid(ui32Base)); in I2CMasterEnable()
314 I2CMasterDisable(uint32_t ui32Base) in I2CMasterDisable() argument
[all …]
Di2s.h273 I2SBaseValid(uint32_t ui32Base) in I2SBaseValid() argument
275 return(ui32Base == I2S0_BASE); in I2SBaseValid()
299 extern void I2SEnable(uint32_t ui32Base);
324 I2SDisable(uint32_t ui32Base) in I2SDisable() argument
327 ASSERT(I2SBaseValid(ui32Base)); in I2SDisable()
376 extern void I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg,
423 extern void I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg,
455 I2SClockConfigure(uint32_t ui32Base, uint32_t ui32ClkConfig) in I2SClockConfigure() argument
458 ASSERT(I2SBaseValid(ui32Base)); in I2SClockConfigure()
490 extern void I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase,
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Dtimer.c79 TimerIntNumberGet(uint32_t ui32Base) in TimerIntNumberGet() argument
85 switch(ui32Base) in TimerIntNumberGet()
113 TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) in TimerConfigure() argument
116 ASSERT(TimerBaseValid(ui32Base)); in TimerConfigure()
143 HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN); in TimerConfigure()
146 HWREG(ui32Base + GPT_O_CFG) = ui32Config >> 24; in TimerConfigure()
150 HWREG(ui32Base + GPT_O_TAMR) = (ui32Config & 0xFF) | GPT_TAMR_TAPWMIE; in TimerConfigure()
151 HWREG(ui32Base + GPT_O_TBMR) = in TimerConfigure()
161 TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) in TimerLevelControl() argument
164 ASSERT(TimerBaseValid(ui32Base)); in TimerLevelControl()
[all …]

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