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Searched refs:divider (Results 1 – 10 of 10) sorted by relevance

/hal_ti-latest/simplelink/source/ti/devices/msp432p4xx/driverlib/
Dlcd_f.c81 uint_fast16_t divider, uint_fast16_t mode) in LCD_F_setBlinkingControl() argument
86 | divider; in LCD_F_setBlinkingControl()
90 uint_fast16_t divider, uint_fast16_t frames) in LCD_F_setAnimationControl() argument
94 | LCD_F_ANMCTL_ANMSTP_MASK)) | clockPrescalar | divider in LCD_F_setAnimationControl()
Dcs.c52 bool _CSIsClockDividerValid(uint8_t divider) in _CSIsClockDividerValid() argument
54 return ((divider == CS_CLOCK_DIVIDER_1) || (divider == CS_CLOCK_DIVIDER_2) in _CSIsClockDividerValid()
55 || (divider == CS_CLOCK_DIVIDER_4) || (divider == CS_CLOCK_DIVIDER_8) in _CSIsClockDividerValid()
56 || (divider == CS_CLOCK_DIVIDER_16) || (divider == CS_CLOCK_DIVIDER_32) in _CSIsClockDividerValid()
57 || (divider == CS_CLOCK_DIVIDER_64) || (divider == CS_CLOCK_DIVIDER_128)); in _CSIsClockDividerValid()
Dlcd_f.h572 uint_fast16_t divider, uint_fast16_t mode);
616 uint_fast16_t divider,
Drom.h2716 uint_fast16_t divider, \
2722 uint_fast16_t divider, \
/hal_ti-latest/simplelink_lpf3/source/ti/devices/cc23x0r5/driverlib/
Dlpcmp.h332 __STATIC_INLINE void LPCMPSetDividerRatio(uint32_t divider) in LPCMPSetDividerRatio() argument
337 …HWREG(SYS0_BASE + SYS0_O_LPCMPCFG) = (lpcmpcfg & ~SYS0_LPCMPCFG_DIV_M) | (divider & SYS0_LPCMPCFG_… in LPCMPSetDividerRatio()
/hal_ti-latest/simplelink/source/ti/devices/msp432p4xx/startup_system_files/
Dsystem_msp432p4111.c104 uint32_t source, divider; in SystemCoreClockUpdate() local
112 divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; in SystemCoreClockUpdate()
113 dividerValue = 1 << divider; in SystemCoreClockUpdate()
Dsystem_msp432p411v.c104 uint32_t source, divider; in SystemCoreClockUpdate() local
112 divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; in SystemCoreClockUpdate()
113 dividerValue = 1 << divider; in SystemCoreClockUpdate()
Dsystem_msp432p411y.c104 uint32_t source, divider; in SystemCoreClockUpdate() local
112 divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; in SystemCoreClockUpdate()
113 dividerValue = 1 << divider; in SystemCoreClockUpdate()
Dsystem_msp432p401m.c104 uint32_t source, divider; in SystemCoreClockUpdate() local
112 divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; in SystemCoreClockUpdate()
113 dividerValue = 1 << divider; in SystemCoreClockUpdate()
Dsystem_msp432p401r.c104 uint32_t source, divider; in SystemCoreClockUpdate() local
112 divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; in SystemCoreClockUpdate()
113 dividerValue = 1 << divider; in SystemCoreClockUpdate()