1 /****************************************************************************** 2 * Filename: hw_uart_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_UART_H__ 34 #define __HW_UART_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // UART component 40 // 41 //***************************************************************************** 42 // Data 43 #define UART_O_DR 0x00000000U 44 45 // Status 46 #define UART_O_RSR_ECR 0x00000004U 47 48 // Flag 49 #define UART_O_FR 0x00000018U 50 51 // IrDA Low-Power Counter Register 52 #define UART_O_UARTILPR 0x00000020U 53 54 // Integer Baud-Rate Divisor 55 #define UART_O_IBRD 0x00000024U 56 57 // Fractional Baud-Rate Divisor 58 #define UART_O_FBRD 0x00000028U 59 60 // Line Control 61 #define UART_O_LCRH 0x0000002CU 62 63 // Control 64 #define UART_O_CTL 0x00000030U 65 66 // Interrupt FIFO Level Select 67 #define UART_O_IFLS 0x00000034U 68 69 // Interrupt Mask Set/Clear 70 #define UART_O_IMSC 0x00000038U 71 72 // Raw Interrupt Status 73 #define UART_O_RIS 0x0000003CU 74 75 // Masked Interrupt Status 76 #define UART_O_MIS 0x00000040U 77 78 // Interrupt Clear 79 #define UART_O_ICR 0x00000044U 80 81 // DMA Control 82 #define UART_O_DMACTL 0x00000048U 83 84 //***************************************************************************** 85 // 86 // Register: UART_O_DR 87 // 88 //***************************************************************************** 89 // Field: [11] OE 90 // 91 // UART Overrun Error: 92 // This bit is set to 1 if data is received and the receive FIFO is already 93 // full. The FIFO contents remain valid because no more data is written when 94 // the FIFO is full, only the contents of the shift register are overwritten. 95 // This is cleared to 0 once there is an empty space in the FIFO and a new 96 // character can be written to it. 97 #define UART_DR_OE 0x00000800U 98 #define UART_DR_OE_M 0x00000800U 99 #define UART_DR_OE_S 11U 100 101 // Field: [10] BE 102 // 103 // UART Break Error: 104 // This bit is set to 1 if a break condition was detected, indicating that the 105 // received data input (UARTRXD input pin) was held LOW for longer than a 106 // full-word transmission time (defined as start, data, parity and stop bits). 107 // In FIFO mode, this error is associated with the character at the top of the 108 // FIFO (i.e., the oldest received data character since last read). When a 109 // break occurs, a 0 character is loaded into the FIFO. The next character is 110 // enabled after the receive data input (UARTRXD input pin) goes to a 1 111 // (marking state), and the next valid start bit is received. 112 #define UART_DR_BE 0x00000400U 113 #define UART_DR_BE_M 0x00000400U 114 #define UART_DR_BE_S 10U 115 116 // Field: [9] PE 117 // 118 // UART Parity Error: 119 // When set to 1, it indicates that the parity of the received data character 120 // does not match the parity that the LCRH.EPS and LCRH.SPS select. 121 // In FIFO mode, this error is associated with the character at the top of the 122 // FIFO (i.e., the oldest received data character since last read). 123 #define UART_DR_PE 0x00000200U 124 #define UART_DR_PE_M 0x00000200U 125 #define UART_DR_PE_S 9U 126 127 // Field: [8] FE 128 // 129 // UART Framing Error: 130 // When set to 1, it indicates that the received character did not have a valid 131 // stop bit (a valid stop bit is 1). 132 // In FIFO mode, this error is associated with the character at the top of the 133 // FIFO (i.e., the oldest received data character since last read). 134 #define UART_DR_FE 0x00000100U 135 #define UART_DR_FE_M 0x00000100U 136 #define UART_DR_FE_S 8U 137 138 // Field: [7:0] DATA 139 // 140 // Data transmitted or received: 141 // On writes, the transmit data character is pushed into the FIFO. 142 // On reads, the oldest received data character since the last read is 143 // returned. 144 #define UART_DR_DATA_W 8U 145 #define UART_DR_DATA_M 0x000000FFU 146 #define UART_DR_DATA_S 0U 147 148 //***************************************************************************** 149 // 150 // Register: UART_O_RSR_ECR 151 // 152 //***************************************************************************** 153 // Field: [3] OE 154 // 155 // UART Overrun Error: 156 // This bit is set to 1 if data is received and the receive FIFO is already 157 // full. The FIFO contents remain valid because no more data is written when 158 // the FIFO is full, only the contents of the shift register are overwritten. 159 // This is cleared to 0 once there is an empty space in the FIFO and a new 160 // character can be written to it. 161 // ENUMs: 162 // CLEAR_ERROR_1 Clears error flag if error is set. Write value is 163 // not important. 164 // ERROR_NOTSET Error flag is not set 165 #define UART_RSR_ECR_OE 0x00000008U 166 #define UART_RSR_ECR_OE_M 0x00000008U 167 #define UART_RSR_ECR_OE_S 3U 168 #define UART_RSR_ECR_OE_CLEAR_ERROR_1 0x00000008U 169 #define UART_RSR_ECR_OE_ERROR_NOTSET 0x00000000U 170 171 // Field: [2] BE 172 // 173 // UART Break Error: 174 // This bit is set to 1 if a break condition was detected, indicating that the 175 // received data input (UARTRXD input pin) was held LOW for longer than a 176 // full-word transmission time (defined as start, data, parity and stop bits). 177 // When a break occurs, a 0 character is loaded into the FIFO. The next 178 // character is enabled after the receive data input (UARTRXD input pin) goes 179 // to a 1 (marking state), and the next valid start bit is received. 180 // ENUMs: 181 // CLEAR_ERROR_1 Clears error flag if error is set. Write value is 182 // not important. 183 // ERROR_NOTSET Error flag is not set 184 #define UART_RSR_ECR_BE 0x00000004U 185 #define UART_RSR_ECR_BE_M 0x00000004U 186 #define UART_RSR_ECR_BE_S 2U 187 #define UART_RSR_ECR_BE_CLEAR_ERROR_1 0x00000004U 188 #define UART_RSR_ECR_BE_ERROR_NOTSET 0x00000000U 189 190 // Field: [1] PE 191 // 192 // UART Parity Error: 193 // When set to 1, it indicates that the parity of the received data character 194 // does not match the parity that the LCRH.EPS and LCRH.SPS select. 195 // ENUMs: 196 // CLEAR_ERROR_1 Clears error flag if error is set. Write value is 197 // not important. 198 // ERROR_NOTSET Error flag is not set 199 #define UART_RSR_ECR_PE 0x00000002U 200 #define UART_RSR_ECR_PE_M 0x00000002U 201 #define UART_RSR_ECR_PE_S 1U 202 #define UART_RSR_ECR_PE_CLEAR_ERROR_1 0x00000002U 203 #define UART_RSR_ECR_PE_ERROR_NOTSET 0x00000000U 204 205 // Field: [0] FE 206 // 207 // UART Framing Error: 208 // When set to 1, it indicates that the received character did not have a valid 209 // stop bit (a valid stop bit is 1). 210 // ENUMs: 211 // CLEAR_ERROR_1 Clears error flag if error is set. Write value is 212 // not important. 213 // ERROR_NOTSET Error flag is not set 214 #define UART_RSR_ECR_FE 0x00000001U 215 #define UART_RSR_ECR_FE_M 0x00000001U 216 #define UART_RSR_ECR_FE_S 0U 217 #define UART_RSR_ECR_FE_CLEAR_ERROR_1 0x00000001U 218 #define UART_RSR_ECR_FE_ERROR_NOTSET 0x00000000U 219 220 //***************************************************************************** 221 // 222 // Register: UART_O_FR 223 // 224 //***************************************************************************** 225 // Field: [7] TXFE 226 // 227 // UART Transmit FIFO Empty: 228 // The meaning of this bit depends on the state of LCRH.FEN . 229 // - If the FIFO is disabled, this bit is set when the transmit holding 230 // register is empty. 231 // - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. 232 // This bit does not indicate if there is data in the transmit shift register. 233 #define UART_FR_TXFE 0x00000080U 234 #define UART_FR_TXFE_M 0x00000080U 235 #define UART_FR_TXFE_S 7U 236 237 // Field: [6] RXFF 238 // 239 // UART Receive FIFO Full: 240 // The meaning of this bit depends on the state of LCRH.FEN. 241 // - If the FIFO is disabled, this bit is set when the receive holding 242 // register is full. 243 // - If the FIFO is enabled, this bit is set when the receive FIFO is full. 244 #define UART_FR_RXFF 0x00000040U 245 #define UART_FR_RXFF_M 0x00000040U 246 #define UART_FR_RXFF_S 6U 247 248 // Field: [5] TXFF 249 // 250 // UART Transmit FIFO Full: 251 // Transmit FIFO full. The meaning of this bit depends on the state of 252 // LCRH.FEN. 253 // - If the FIFO is disabled, this bit is set when the transmit holding 254 // register is full. 255 // - If the FIFO is enabled, this bit is set when the transmit FIFO is full. 256 #define UART_FR_TXFF 0x00000020U 257 #define UART_FR_TXFF_M 0x00000020U 258 #define UART_FR_TXFF_S 5U 259 260 // Field: [4] RXFE 261 // 262 // UART Receive FIFO Empty: 263 // Receive FIFO empty. The meaning of this bit depends on the state of 264 // LCRH.FEN. 265 // - If the FIFO is disabled, this bit is set when the receive holding 266 // register is empty. 267 // - If the FIFO is enabled, this bit is set when the receive FIFO is empty. 268 #define UART_FR_RXFE 0x00000010U 269 #define UART_FR_RXFE_M 0x00000010U 270 #define UART_FR_RXFE_S 4U 271 272 // Field: [3] BUSY 273 // 274 // UART Busy: 275 // If this bit is set to 1, the UART is busy transmitting data. This bit 276 // remains set until the complete byte, including all the stop bits, has been 277 // sent from the shift register. 278 // This bit is set as soon as the transmit FIFO becomes non-empty, regardless 279 // of whether the UART is enabled or not. 280 #define UART_FR_BUSY 0x00000008U 281 #define UART_FR_BUSY_M 0x00000008U 282 #define UART_FR_BUSY_S 3U 283 284 // Field: [0] CTS 285 // 286 // Clear To Send: 287 // This bit is the complement of the active-low UART CTS input pin. 288 // That is, the bit is 1 when CTS input pin is LOW. 289 #define UART_FR_CTS 0x00000001U 290 #define UART_FR_CTS_M 0x00000001U 291 #define UART_FR_CTS_S 0U 292 293 //***************************************************************************** 294 // 295 // Register: UART_O_UARTILPR 296 // 297 //***************************************************************************** 298 // Field: [7:0] ILPDVSR 299 // 300 // 8 bit low-power divisor value. In low-power IrDA mode the UART rejects 301 // random noise on the received serial data 302 // input by ignoring SIRIN pulses that are less than 3 periods of IrLPBaud16. 303 #define UART_UARTILPR_ILPDVSR_W 8U 304 #define UART_UARTILPR_ILPDVSR_M 0x000000FFU 305 #define UART_UARTILPR_ILPDVSR_S 0U 306 307 //***************************************************************************** 308 // 309 // Register: UART_O_IBRD 310 // 311 //***************************************************************************** 312 // Field: [15:0] DIVINT 313 // 314 // The integer baud rate divisor: 315 // The baud rate divisor is calculated using the formula below: 316 // Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) 317 // Baud rate divisor must be minimum 1 and maximum 65535. 318 // That is, DIVINT=0 does not give a valid baud rate. 319 // Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be 320 // illegal. 321 // Refer to Section 19.1.5 for an example calculation. 322 // A valid value must be written to this field before the UART can be used for 323 // RX or TX operations. 324 #define UART_IBRD_DIVINT_W 16U 325 #define UART_IBRD_DIVINT_M 0x0000FFFFU 326 #define UART_IBRD_DIVINT_S 0U 327 328 //***************************************************************************** 329 // 330 // Register: UART_O_FBRD 331 // 332 //***************************************************************************** 333 // Field: [5:0] DIVFRAC 334 // 335 // Fractional Baud-Rate Divisor: 336 // The baud rate divisor is calculated using the formula below: 337 // Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) 338 // Baud rate divisor must be minimum 1 and maximum 65535. 339 // That is, IBRD.DIVINT=0 does not give a valid baud rate. 340 // Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be 341 // illegal. 342 // Refer to Section 19.1.5 for an example calculation. 343 // A valid value must be written to this field before the UART can be used for 344 // RX or TX operations. 345 #define UART_FBRD_DIVFRAC_W 6U 346 #define UART_FBRD_DIVFRAC_M 0x0000003FU 347 #define UART_FBRD_DIVFRAC_S 0U 348 349 //***************************************************************************** 350 // 351 // Register: UART_O_LCRH 352 // 353 //***************************************************************************** 354 // Field: [7] SPS 355 // 356 // UART Stick Parity Select: 357 // 358 // 0: Stick parity is disabled 359 // 1: The parity bit is transmitted and checked as invert of EPS field (i.e. 360 // the parity bit is transmitted and checked as 1 when EPS = 0). 361 // 362 // This bit has no effect when PEN disables parity checking and generation. 363 #define UART_LCRH_SPS 0x00000080U 364 #define UART_LCRH_SPS_M 0x00000080U 365 #define UART_LCRH_SPS_S 7U 366 367 // Field: [6:5] WLEN 368 // 369 // UART Word Length: 370 // These bits indicate the number of data bits transmitted or received in a 371 // frame. 372 // ENUMs: 373 // BITL8 Word Length 8 bits 374 // BITL7 Word Length 7 bits 375 // BITL6 Word Length 6 bits 376 // BITL5 Word Length 5 bits 377 #define UART_LCRH_WLEN_W 2U 378 #define UART_LCRH_WLEN_M 0x00000060U 379 #define UART_LCRH_WLEN_S 5U 380 #define UART_LCRH_WLEN_BITL8 0x00000060U 381 #define UART_LCRH_WLEN_BITL7 0x00000040U 382 #define UART_LCRH_WLEN_BITL6 0x00000020U 383 #define UART_LCRH_WLEN_BITL5 0x00000000U 384 385 // Field: [4] FEN 386 // 387 // UART Enable FIFOs 388 // ENUMs: 389 // EN Transmit and receive FIFO buffers are enabled 390 // (FIFO mode) 391 // DIS FIFOs are disabled (character mode) that is, the 392 // FIFOs become 1-byte-deep holding registers. 393 #define UART_LCRH_FEN 0x00000010U 394 #define UART_LCRH_FEN_M 0x00000010U 395 #define UART_LCRH_FEN_S 4U 396 #define UART_LCRH_FEN_EN 0x00000010U 397 #define UART_LCRH_FEN_DIS 0x00000000U 398 399 // Field: [3] STP2 400 // 401 // UART Two Stop Bits Select: 402 // If this bit is set to 1, two stop bits are transmitted at the end of the 403 // frame. The receive logic does not check for two stop bits being received. 404 #define UART_LCRH_STP2 0x00000008U 405 #define UART_LCRH_STP2_M 0x00000008U 406 #define UART_LCRH_STP2_S 3U 407 408 // Field: [2] EPS 409 // 410 // UART Even Parity Select 411 // ENUMs: 412 // EVEN Even parity: The UART generates or checks for an 413 // even number of 1s in the data and parity bits. 414 // ODD Odd parity: The UART generates or checks for an 415 // odd number of 1s in the data and parity bits. 416 #define UART_LCRH_EPS 0x00000004U 417 #define UART_LCRH_EPS_M 0x00000004U 418 #define UART_LCRH_EPS_S 2U 419 #define UART_LCRH_EPS_EVEN 0x00000004U 420 #define UART_LCRH_EPS_ODD 0x00000000U 421 422 // Field: [1] PEN 423 // 424 // UART Parity Enable 425 // This bit controls generation and checking of parity bit. 426 // ENUMs: 427 // EN Parity checking and generation is enabled. 428 // DIS Parity is disabled and no parity bit is added to 429 // the data frame 430 #define UART_LCRH_PEN 0x00000002U 431 #define UART_LCRH_PEN_M 0x00000002U 432 #define UART_LCRH_PEN_S 1U 433 #define UART_LCRH_PEN_EN 0x00000002U 434 #define UART_LCRH_PEN_DIS 0x00000000U 435 436 // Field: [0] BRK 437 // 438 // UART Send Break 439 // If this bit is set to 1, a low-level is continually output on the UARTTXD 440 // output pin, after completing transmission of the current character. For the 441 // proper execution of the break command, the 442 // software must set this bit for at least two complete frames. For normal use, 443 // this bit must be cleared to 0. 444 #define UART_LCRH_BRK 0x00000001U 445 #define UART_LCRH_BRK_M 0x00000001U 446 #define UART_LCRH_BRK_S 0U 447 448 //***************************************************************************** 449 // 450 // Register: UART_O_CTL 451 // 452 //***************************************************************************** 453 // Field: [15] CTSEN 454 // 455 // CTS hardware flow control enable 456 // ENUMs: 457 // EN CTS hardware flow control enabled 458 // DIS CTS hardware flow control disabled 459 #define UART_CTL_CTSEN 0x00008000U 460 #define UART_CTL_CTSEN_M 0x00008000U 461 #define UART_CTL_CTSEN_S 15U 462 #define UART_CTL_CTSEN_EN 0x00008000U 463 #define UART_CTL_CTSEN_DIS 0x00000000U 464 465 // Field: [14] RTSEN 466 // 467 // RTS hardware flow control enable 468 // ENUMs: 469 // EN RTS hardware flow control enabled 470 // DIS RTS hardware flow control disabled 471 #define UART_CTL_RTSEN 0x00004000U 472 #define UART_CTL_RTSEN_M 0x00004000U 473 #define UART_CTL_RTSEN_S 14U 474 #define UART_CTL_RTSEN_EN 0x00004000U 475 #define UART_CTL_RTSEN_DIS 0x00000000U 476 477 // Field: [11] RTS 478 // 479 // Request to Send 480 // This bit is the complement of the active-low UART RTS output. That is, when 481 // the bit is programmed to a 1 then RTS output on the pins is LOW. 482 #define UART_CTL_RTS 0x00000800U 483 #define UART_CTL_RTS_M 0x00000800U 484 #define UART_CTL_RTS_S 11U 485 486 // Field: [9] RXE 487 // 488 // UART Receive Enable 489 // If the UART is disabled in the middle of reception, it completes the current 490 // character before stopping. 491 // ENUMs: 492 // EN UART Receive enabled 493 // DIS UART Receive disabled 494 #define UART_CTL_RXE 0x00000200U 495 #define UART_CTL_RXE_M 0x00000200U 496 #define UART_CTL_RXE_S 9U 497 #define UART_CTL_RXE_EN 0x00000200U 498 #define UART_CTL_RXE_DIS 0x00000000U 499 500 // Field: [8] TXE 501 // 502 // UART Transmit Enable 503 // If the UART is disabled in the middle of transmission, it completes the 504 // current character before stopping. 505 // ENUMs: 506 // EN UART Transmit enabled 507 // DIS UART Transmit disabled 508 #define UART_CTL_TXE 0x00000100U 509 #define UART_CTL_TXE_M 0x00000100U 510 #define UART_CTL_TXE_S 8U 511 #define UART_CTL_TXE_EN 0x00000100U 512 #define UART_CTL_TXE_DIS 0x00000000U 513 514 // Field: [7] LBE 515 // 516 // UART Loop Back Enable 517 // Enabling the loop-back mode connects the UARTTXD output from the UART to 518 // UARTRXD input of the UART. 519 // ENUMs: 520 // EN Loop Back enabled 521 // DIS Loop Back disabled 522 #define UART_CTL_LBE 0x00000080U 523 #define UART_CTL_LBE_M 0x00000080U 524 #define UART_CTL_LBE_S 7U 525 #define UART_CTL_LBE_EN 0x00000080U 526 #define UART_CTL_LBE_DIS 0x00000000U 527 528 // Field: [6] FCEN 529 // 530 // UART FIFO Concatenation Enable 531 // Enabling the FIFO concatenation in TX mode resulting in 16 TX buffers. 532 // ENUMs: 533 // EN UART FIFO Concatenation enabled 534 // DIS UART FIFO Concatenation disabled 535 #define UART_CTL_FCEN 0x00000040U 536 #define UART_CTL_FCEN_M 0x00000040U 537 #define UART_CTL_FCEN_S 6U 538 #define UART_CTL_FCEN_EN 0x00000040U 539 #define UART_CTL_FCEN_DIS 0x00000000U 540 541 // Field: [2] SIRLP 542 // 543 // SIR low power IrDA mode 544 // This bit selects the IrDA encoding mode 545 // ENUMs: 546 // EN Low-level bits are transmitted with a pulse width 547 // of 3 times the period of IrLPBaud16(which has a 548 // frequency of (UARTCLK 549 // frequency)/UARTILP.ILPDVSR), regardless of the 550 // selected bit rate. 551 // In low-power IrDA mode 552 // the UART rejects random noise on the received 553 // serial data 554 // input by ignoring SIRIN 555 // pulses that are less than 3 periods of 556 // IrLPBaud16. 557 // DIS Low-level bits are transmitted as active high with 558 // a 3/16th period width, 559 #define UART_CTL_SIRLP 0x00000004U 560 #define UART_CTL_SIRLP_M 0x00000004U 561 #define UART_CTL_SIRLP_S 2U 562 #define UART_CTL_SIRLP_EN 0x00000004U 563 #define UART_CTL_SIRLP_DIS 0x00000000U 564 565 // Field: [1] SIREN 566 // 567 // SIR Enable 568 // This bit has no effect if UARTEN bit disables the UART. 569 // ENUMs: 570 // EN IrDA SIR ENDEC is enabled. Data is transmitted and 571 // received via nSIROUT and SIRIN. 572 // DIS IrDA SIR ENDEC is disabled 573 #define UART_CTL_SIREN 0x00000002U 574 #define UART_CTL_SIREN_M 0x00000002U 575 #define UART_CTL_SIREN_S 1U 576 #define UART_CTL_SIREN_EN 0x00000002U 577 #define UART_CTL_SIREN_DIS 0x00000000U 578 579 // Field: [0] UARTEN 580 // 581 // UART Enable 582 // ENUMs: 583 // EN UART enabled 584 // DIS UART disabled 585 #define UART_CTL_UARTEN 0x00000001U 586 #define UART_CTL_UARTEN_M 0x00000001U 587 #define UART_CTL_UARTEN_S 0U 588 #define UART_CTL_UARTEN_EN 0x00000001U 589 #define UART_CTL_UARTEN_DIS 0x00000000U 590 591 //***************************************************************************** 592 // 593 // Register: UART_O_IFLS 594 // 595 //***************************************************************************** 596 // Field: [5:3] RXSEL 597 // 598 // Receive interrupt FIFO level select: 599 // This field sets the trigger points for the receive interrupt. Values 600 // 0b101-0b111 are reserved. 601 // ENUMs: 602 // THREEQU Receive FIFO becomes >= 3/4 full 603 // HALF Receive FIFO becomes >= 1/2 full 604 // QUARTER Receive FIFO becomes >= 1/4 full 605 #define UART_IFLS_RXSEL_W 3U 606 #define UART_IFLS_RXSEL_M 0x00000038U 607 #define UART_IFLS_RXSEL_S 3U 608 #define UART_IFLS_RXSEL_THREEQU 0x00000018U 609 #define UART_IFLS_RXSEL_HALF 0x00000010U 610 #define UART_IFLS_RXSEL_QUARTER 0x00000008U 611 612 // Field: [2:0] TXSEL 613 // 614 // Transmit interrupt FIFO level select: 615 // This field sets the trigger points for the transmit interrupt. Values 616 // 0b101-0b111 are reserved. 617 // ENUMs: 618 // THREEQU Transmit FIFO becomes <= 3/4 full 619 // HALF Transmit FIFO becomes <= 1/2 full 620 // QUARTER Transmit FIFO becomes <= 1/4 full 621 #define UART_IFLS_TXSEL_W 3U 622 #define UART_IFLS_TXSEL_M 0x00000007U 623 #define UART_IFLS_TXSEL_S 0U 624 #define UART_IFLS_TXSEL_THREEQU 0x00000003U 625 #define UART_IFLS_TXSEL_HALF 0x00000002U 626 #define UART_IFLS_TXSEL_QUARTER 0x00000001U 627 628 //***************************************************************************** 629 // 630 // Register: UART_O_IMSC 631 // 632 //***************************************************************************** 633 // Field: [13] RXDMADONE 634 // 635 // RX DMA done interrupt mask. A read returns the current mask for UART's 636 // RXDMADONE interrupt. On a write of 1, the mask of the RXDMADONE interrupt is 637 // set which means the interrupt state will be reflected in MIS.RXDMADONE. A 638 // write of 0 clears the mask which means MIS.RXDMADONE will not reflect the 639 // interrupt. 640 #define UART_IMSC_RXDMADONE 0x00002000U 641 #define UART_IMSC_RXDMADONE_M 0x00002000U 642 #define UART_IMSC_RXDMADONE_S 13U 643 644 // Field: [12] TXDMADONE 645 // 646 // TX DMA done interrupt mask. A read returns the current mask for UART's 647 // TXDMADONE interrupt. On a write of 1, the mask of the TXDMADONE interrupt is 648 // set which means the interrupt state will be reflected in MIS.TXDMADONE. A 649 // write of 0 clears the mask which means MIS.TXDMADONE will not reflect the 650 // interrupt. 651 #define UART_IMSC_TXDMADONE 0x00001000U 652 #define UART_IMSC_TXDMADONE_M 0x00001000U 653 #define UART_IMSC_TXDMADONE_S 12U 654 655 // Field: [11] EOT 656 // 657 // End of Transmission interrupt mask. A read returns the current mask for 658 // UART's EoT interrupt. On a write of 1, the mask of the EoT interrupt is set 659 // which means the interrupt state will be reflected in MIS.EOT. A write of 0 660 // clears the mask which means MIS.EOT will not reflect the interrupt. 661 #define UART_IMSC_EOT 0x00000800U 662 #define UART_IMSC_EOT_M 0x00000800U 663 #define UART_IMSC_EOT_S 11U 664 665 // Field: [10] OE 666 // 667 // Overrun error interrupt mask. A read returns the current mask for UART's 668 // overrun error interrupt. On a write of 1, the mask of the overrun error 669 // interrupt is set which means the interrupt state will be reflected in 670 // MIS.OE. A write of 0 clears the mask which means MIS.OE will not reflect the 671 // interrupt. 672 #define UART_IMSC_OE 0x00000400U 673 #define UART_IMSC_OE_M 0x00000400U 674 #define UART_IMSC_OE_S 10U 675 676 // Field: [9] BE 677 // 678 // Break error interrupt mask. A read returns the current mask for UART's break 679 // error interrupt. On a write of 1, the mask of the overrun error interrupt is 680 // set which means the interrupt state will be reflected in MIS.BE. A write of 681 // 0 clears the mask which means MIS.BE will not reflect the interrupt. 682 #define UART_IMSC_BE 0x00000200U 683 #define UART_IMSC_BE_M 0x00000200U 684 #define UART_IMSC_BE_S 9U 685 686 // Field: [8] PE 687 // 688 // Parity error interrupt mask. A read returns the current mask for UART's 689 // parity error interrupt. On a write of 1, the mask of the overrun error 690 // interrupt is set which means the interrupt state will be reflected in 691 // MIS.PE. A write of 0 clears the mask which means MIS.PE will not reflect the 692 // interrupt. 693 #define UART_IMSC_PE 0x00000100U 694 #define UART_IMSC_PE_M 0x00000100U 695 #define UART_IMSC_PE_S 8U 696 697 // Field: [7] FE 698 // 699 // Framing error interrupt mask. A read returns the current mask for UART's 700 // framing error interrupt. On a write of 1, the mask of the overrun error 701 // interrupt is set which means the interrupt state will be reflected in 702 // MIS.FE. A write of 0 clears the mask which means MIS.FE will not reflect the 703 // interrupt. 704 #define UART_IMSC_FE 0x00000080U 705 #define UART_IMSC_FE_M 0x00000080U 706 #define UART_IMSC_FE_S 7U 707 708 // Field: [6] RT 709 // 710 // Receive timeout interrupt mask. A read returns the current mask for UART's 711 // receive timeout interrupt. On a write of 1, the mask of the overrun error 712 // interrupt is set which means the interrupt state will be reflected in 713 // MIS.RT. A write of 0 clears the mask which means this bitfield will not 714 // reflect the interrupt. 715 // The raw interrupt for receive timeout RIS.RT cannot be set unless the mask 716 // is set (RT = 1). This is because the mask acts as an enable for power 717 // saving. That is, the same status can be read from MIS.RT and RIS.RT. 718 #define UART_IMSC_RT 0x00000040U 719 #define UART_IMSC_RT_M 0x00000040U 720 #define UART_IMSC_RT_S 6U 721 722 // Field: [5] TX 723 // 724 // Transmit interrupt mask. A read returns the current mask for UART's transmit 725 // interrupt. On a write of 1, the mask of the overrun error interrupt is set 726 // which means the interrupt state will be reflected in MIS.TX. A write of 0 727 // clears the mask which means MIS.TX will not reflect the interrupt. 728 #define UART_IMSC_TX 0x00000020U 729 #define UART_IMSC_TX_M 0x00000020U 730 #define UART_IMSC_TX_S 5U 731 732 // Field: [4] RX 733 // 734 // Receive interrupt mask. A read returns the current mask for UART's receive 735 // interrupt. On a write of 1, the mask of the overrun error interrupt is set 736 // which means the interrupt state will be reflected in MIS.RX. A write of 0 737 // clears the mask which means MIS.RX will not reflect the interrupt. 738 #define UART_IMSC_RX 0x00000010U 739 #define UART_IMSC_RX_M 0x00000010U 740 #define UART_IMSC_RX_S 4U 741 742 // Field: [1] CTSM 743 // 744 // Clear to Send (CTS) modem interrupt mask. A read returns the current mask 745 // for UART's clear to send interrupt. On a write of 1, the mask of the overrun 746 // error interrupt is set which means the interrupt state will be reflected in 747 // MIS.CTSM. A write of 0 clears the mask which means MIS.CTSM will not reflect 748 // the interrupt. 749 #define UART_IMSC_CTSM 0x00000002U 750 #define UART_IMSC_CTSM_M 0x00000002U 751 #define UART_IMSC_CTSM_S 1U 752 753 //***************************************************************************** 754 // 755 // Register: UART_O_RIS 756 // 757 //***************************************************************************** 758 // Field: [13] RXDMADONE 759 // 760 // RX DMA done interrupt status: 761 // This field returns the raw interrupt state of UART's RX DMA done interrupt. 762 // RX DMA done flag is set when you recieve RX DMA done status from dma module. 763 #define UART_RIS_RXDMADONE 0x00002000U 764 #define UART_RIS_RXDMADONE_M 0x00002000U 765 #define UART_RIS_RXDMADONE_S 13U 766 767 // Field: [12] TXDMADONE 768 // 769 // TX DMA done interrupt status: 770 // This field returns the raw interrupt state of UART's TX DMA done interrupt. 771 // TX DMA done flag is set when you recieve TX DMA done status from dma module. 772 #define UART_RIS_TXDMADONE 0x00001000U 773 #define UART_RIS_TXDMADONE_M 0x00001000U 774 #define UART_RIS_TXDMADONE_S 12U 775 776 // Field: [11] EOT 777 // 778 // End of Transmission interrupt status: 779 // This field returns the raw interrupt state of UART's end of transmission 780 // interrupt. End of transmission flag is set when all the Transmit data in the 781 // FIFO and on the TX Line is tranmitted. 782 #define UART_RIS_EOT 0x00000800U 783 #define UART_RIS_EOT_M 0x00000800U 784 #define UART_RIS_EOT_S 11U 785 786 // Field: [10] OE 787 // 788 // Overrun error interrupt status: 789 // This field returns the raw interrupt state of UART's overrun error 790 // interrupt. Overrun error occurs if data is received and the receive FIFO is 791 // full. 792 #define UART_RIS_OE 0x00000400U 793 #define UART_RIS_OE_M 0x00000400U 794 #define UART_RIS_OE_S 10U 795 796 // Field: [9] BE 797 // 798 // Break error interrupt status: 799 // This field returns the raw interrupt state of UART's break error interrupt. 800 // Break error is set when a break condition is detected, indicating that the 801 // received data input (UARTRXD input pin) was held LOW for longer than a 802 // full-word transmission time (defined as start, data, parity and stop bits). 803 #define UART_RIS_BE 0x00000200U 804 #define UART_RIS_BE_M 0x00000200U 805 #define UART_RIS_BE_S 9U 806 807 // Field: [8] PE 808 // 809 // Parity error interrupt status: 810 // This field returns the raw interrupt state of UART's parity error interrupt. 811 // Parity error is set if the parity of the received data character does not 812 // match the parity that the LCRH.EPS and LCRH.SPS select. 813 #define UART_RIS_PE 0x00000100U 814 #define UART_RIS_PE_M 0x00000100U 815 #define UART_RIS_PE_S 8U 816 817 // Field: [7] FE 818 // 819 // Framing error interrupt status: 820 // This field returns the raw interrupt state of UART's framing error 821 // interrupt. Framing error is set if the received character does not have a 822 // valid stop bit (a valid stop bit is 1). 823 #define UART_RIS_FE 0x00000080U 824 #define UART_RIS_FE_M 0x00000080U 825 #define UART_RIS_FE_S 7U 826 827 // Field: [6] RT 828 // 829 // Receive timeout interrupt status: 830 // This field returns the raw interrupt state of UART's receive timeout 831 // interrupt. The receive timeout interrupt is asserted when the receive FIFO 832 // is not empty, and no more data is received during a 32-bit period. The 833 // receive timeout interrupt is cleared either when the FIFO becomes empty 834 // through reading all the data, or when a 1 is written to ICR.RT. 835 // The raw interrupt for receive timeout cannot be set unless the mask is set 836 // (IMSC.RT = 1). This is because the mask acts as an enable for power saving. 837 // That is, the same status can be read from MIS.RT and RT. 838 #define UART_RIS_RT 0x00000040U 839 #define UART_RIS_RT_M 0x00000040U 840 #define UART_RIS_RT_S 6U 841 842 // Field: [5] TX 843 // 844 // Transmit interrupt status: 845 // This field returns the raw interrupt state of UART's transmit interrupt. 846 // When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if 847 // the number of bytes in transmit FIFO is equal to or lower than the 848 // programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by 849 // writing data to the transmit FIFO until it becomes greater than the trigger 850 // level, or by clearing the interrupt through ICR.TX. 851 // When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one 852 // location, the transmit interrupt is asserted if there is no data present in 853 // the transmitters single location. It is cleared by performing a single write 854 // to the transmit FIFO, or by clearing the interrupt through ICR.TX. 855 #define UART_RIS_TX 0x00000020U 856 #define UART_RIS_TX_M 0x00000020U 857 #define UART_RIS_TX_S 5U 858 859 // Field: [4] RX 860 // 861 // Receive interrupt status: 862 // This field returns the raw interrupt state of UART's receive interrupt. 863 // When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if 864 // the receive FIFO reaches the programmed trigger 865 // level (IFLS.RXSEL). The receive interrupt is cleared by reading data from 866 // the receive FIFO until it becomes less than the trigger level, or by 867 // clearing the interrupt through ICR.RX. 868 // When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one 869 // location, the receive interrupt is asserted if data is received 870 // thereby filling the location. The receive interrupt is cleared by performing 871 // a single read of the receive FIFO, or by clearing the interrupt through 872 // ICR.RX. 873 #define UART_RIS_RX 0x00000010U 874 #define UART_RIS_RX_M 0x00000010U 875 #define UART_RIS_RX_S 4U 876 877 // Field: [1] CTSM 878 // 879 // Clear to Send (CTS) modem interrupt status: 880 // This field returns the raw interrupt state of UART's clear to send 881 // interrupt. 882 #define UART_RIS_CTSM 0x00000002U 883 #define UART_RIS_CTSM_M 0x00000002U 884 #define UART_RIS_CTSM_S 1U 885 886 //***************************************************************************** 887 // 888 // Register: UART_O_MIS 889 // 890 //***************************************************************************** 891 // Field: [13] RXDMADONE 892 // 893 // RX DMA done interrupt status: 894 // This field returns the masked interrupt state of the RX DMA done interrupt 895 // which is the bitiwse AND product of raw interrupt state RIS.RXDMADONE and 896 // the mask setting IMSC.RXDMADONE. 897 #define UART_MIS_RXDMADONE 0x00002000U 898 #define UART_MIS_RXDMADONE_M 0x00002000U 899 #define UART_MIS_RXDMADONE_S 13U 900 901 // Field: [12] TXDMADONE 902 // 903 // TX DMA done interrupt status: 904 // This field returns the masked interrupt state of the TX DMA done interrupt 905 // which is the bitwise AND product of raw interrupt state RIS.TXDMADONE and 906 // the mask setting IMSC.TXDMADONE. 907 #define UART_MIS_TXDMADONE 0x00001000U 908 #define UART_MIS_TXDMADONE_M 0x00001000U 909 #define UART_MIS_TXDMADONE_S 12U 910 911 // Field: [11] EOT 912 // 913 // End of Transmission interrupt status: 914 // This field returns the masked interrupt state of the End of transmission 915 // interrupt which is the bitwise AND product of raw interrupt state RIS.EOT 916 // and the mask setting IMSC.EOT. 917 #define UART_MIS_EOT 0x00000800U 918 #define UART_MIS_EOT_M 0x00000800U 919 #define UART_MIS_EOT_S 11U 920 921 // Field: [10] OE 922 // 923 // Overrun error masked interrupt status: 924 // This field returns the masked interrupt state of the overrun interrupt which 925 // is the bitwise AND product of raw interrupt state RIS.OE and the mask 926 // setting IMSC.OE. 927 #define UART_MIS_OE 0x00000400U 928 #define UART_MIS_OE_M 0x00000400U 929 #define UART_MIS_OE_S 10U 930 931 // Field: [9] BE 932 // 933 // Break error masked interrupt status: 934 // This field returns the masked interrupt state of the break error interrupt 935 // which is the bitiwse AND product of raw interrupt state RIS.BE and the mask 936 // setting IMSC.BE. 937 #define UART_MIS_BE 0x00000200U 938 #define UART_MIS_BE_M 0x00000200U 939 #define UART_MIS_BE_S 9U 940 941 // Field: [8] PE 942 // 943 // Parity error masked interrupt status: 944 // This field returns the masked interrupt state of the parity error interrupt 945 // which is the bitiwise AND product of raw interrupt state RIS.PE and the mask 946 // setting IMSC.PE. 947 #define UART_MIS_PE 0x00000100U 948 #define UART_MIS_PE_M 0x00000100U 949 #define UART_MIS_PE_S 8U 950 951 // Field: [7] FE 952 // 953 // Framing error masked interrupt status: Returns the masked interrupt state of 954 // the framing error interrupt which is the bitiwse AND product of raw 955 // interrupt state RIS.FE and the mask setting IMSC.FE. 956 #define UART_MIS_FE 0x00000080U 957 #define UART_MIS_FE_M 0x00000080U 958 #define UART_MIS_FE_S 7U 959 960 // Field: [6] RT 961 // 962 // Receive timeout masked interrupt status: 963 // Returns the masked interrupt state of the receive timeout interrupt. 964 // The raw interrupt for receive timeout cannot be set unless the mask is set 965 // (IMSC.RT = 1). This is because the mask acts as an enable for power saving. 966 // That is, the same status can be read from MIS.RT and RIS.RT. 967 #define UART_MIS_RT 0x00000040U 968 #define UART_MIS_RT_M 0x00000040U 969 #define UART_MIS_RT_S 6U 970 971 // Field: [5] TX 972 // 973 // Transmit masked interrupt status: 974 // This field returns the masked interrupt state of the transmit interrupt 975 // which is the bitiwse AND product of raw interrupt state RIS.TX and the mask 976 // setting IMSC.TX. 977 #define UART_MIS_TX 0x00000020U 978 #define UART_MIS_TX_M 0x00000020U 979 #define UART_MIS_TX_S 5U 980 981 // Field: [4] RX 982 // 983 // Receive masked interrupt status: 984 // This field returns the masked interrupt state of the receive interrupt 985 // which is the bitwise AND product of raw interrupt state RIS.RX and the mask 986 // setting IMSC.RX. 987 #define UART_MIS_RX 0x00000010U 988 #define UART_MIS_RX_M 0x00000010U 989 #define UART_MIS_RX_S 4U 990 991 // Field: [1] CTSM 992 // 993 // Clear to Send (CTS) modem masked interrupt status: 994 // This field returns the masked interrupt state of the clear to send interrupt 995 // which is the bitwise AND product of raw interrupt state RIS.CTS and the mask 996 // setting IMSC.CTS. 997 #define UART_MIS_CTSM 0x00000002U 998 #define UART_MIS_CTSM_M 0x00000002U 999 #define UART_MIS_CTSM_S 1U 1000 1001 //***************************************************************************** 1002 // 1003 // Register: UART_O_ICR 1004 // 1005 //***************************************************************************** 1006 // Field: [13] RXDMADONE 1007 // 1008 // RX DMA Done interrupt clear: 1009 // Writing 1 to this field clears the RX DMA done interrupt (RIS.RXDMADONE). 1010 // Writing 0 has no effect. 1011 #define UART_ICR_RXDMADONE 0x00002000U 1012 #define UART_ICR_RXDMADONE_M 0x00002000U 1013 #define UART_ICR_RXDMADONE_S 13U 1014 1015 // Field: [12] TXDMADONE 1016 // 1017 // TX DMA Done interrupt clear: 1018 // Writing 1 to this field clears the TX DMA done interrupt (RIS.TXDMADONE). 1019 // Writing 0 has no effect. 1020 #define UART_ICR_TXDMADONE 0x00001000U 1021 #define UART_ICR_TXDMADONE_M 0x00001000U 1022 #define UART_ICR_TXDMADONE_S 12U 1023 1024 // Field: [11] EOT 1025 // 1026 // End of Transmission interrupt clear: 1027 // Writing 1 to this field clears the End of Transmission interrupt (RIS.EOT). 1028 // Writing 0 has no effect. 1029 #define UART_ICR_EOT 0x00000800U 1030 #define UART_ICR_EOT_M 0x00000800U 1031 #define UART_ICR_EOT_S 11U 1032 1033 // Field: [10] OE 1034 // 1035 // Overrun error interrupt clear: 1036 // Writing 1 to this field clears the overrun error interrupt (RIS.OE). Writing 1037 // 0 has no effect. 1038 #define UART_ICR_OE 0x00000400U 1039 #define UART_ICR_OE_M 0x00000400U 1040 #define UART_ICR_OE_S 10U 1041 1042 // Field: [9] BE 1043 // 1044 // Break error interrupt clear: 1045 // Writing 1 to this field clears the break error interrupt (RIS.BE). Writing 0 1046 // has no effect. 1047 #define UART_ICR_BE 0x00000200U 1048 #define UART_ICR_BE_M 0x00000200U 1049 #define UART_ICR_BE_S 9U 1050 1051 // Field: [8] PE 1052 // 1053 // Parity error interrupt clear: 1054 // Writing 1 to this field clears the parity error interrupt (RIS.PE). Writing 1055 // 0 has no effect. 1056 #define UART_ICR_PE 0x00000100U 1057 #define UART_ICR_PE_M 0x00000100U 1058 #define UART_ICR_PE_S 8U 1059 1060 // Field: [7] FE 1061 // 1062 // Framing error interrupt clear: 1063 // Writing 1 to this field clears the framing error interrupt (RIS.FE). Writing 1064 // 0 has no effect. 1065 #define UART_ICR_FE 0x00000080U 1066 #define UART_ICR_FE_M 0x00000080U 1067 #define UART_ICR_FE_S 7U 1068 1069 // Field: [6] RT 1070 // 1071 // Receive timeout interrupt clear: 1072 // Writing 1 to this field clears the receive timeout interrupt (RIS.RT). 1073 // Writing 0 has no effect. 1074 #define UART_ICR_RT 0x00000040U 1075 #define UART_ICR_RT_M 0x00000040U 1076 #define UART_ICR_RT_S 6U 1077 1078 // Field: [5] TX 1079 // 1080 // Transmit interrupt clear: 1081 // Writing 1 to this field clears the transmit interrupt (RIS.TX). Writing 0 1082 // has no effect. 1083 #define UART_ICR_TX 0x00000020U 1084 #define UART_ICR_TX_M 0x00000020U 1085 #define UART_ICR_TX_S 5U 1086 1087 // Field: [4] RX 1088 // 1089 // Receive interrupt clear: 1090 // Writing 1 to this field clears the receive interrupt (RIS.RX). Writing 0 has 1091 // no effect. 1092 #define UART_ICR_RX 0x00000010U 1093 #define UART_ICR_RX_M 0x00000010U 1094 #define UART_ICR_RX_S 4U 1095 1096 // Field: [1] CTSM 1097 // 1098 // Clear to Send (CTS) modem interrupt clear: 1099 // Writing 1 to this field clears the clear to send interrupt (RIS.CTS). 1100 // Writing 0 has no effect. 1101 #define UART_ICR_CTSM 0x00000002U 1102 #define UART_ICR_CTSM_M 0x00000002U 1103 #define UART_ICR_CTSM_S 1U 1104 1105 //***************************************************************************** 1106 // 1107 // Register: UART_O_DMACTL 1108 // 1109 //***************************************************************************** 1110 // Field: [2] DMAONERR 1111 // 1112 // DMA on error. If this bit is set to 1, the DMA receive request outputs (for 1113 // single and burst requests) are disabled when the UART error interrupt is 1114 // asserted (more specifically if any of the error interrupts RIS.PERIS, 1115 // RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). 1116 #define UART_DMACTL_DMAONERR 0x00000004U 1117 #define UART_DMACTL_DMAONERR_M 0x00000004U 1118 #define UART_DMACTL_DMAONERR_S 2U 1119 1120 // Field: [1] TXDMAE 1121 // 1122 // Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is 1123 // enabled. 1124 #define UART_DMACTL_TXDMAE 0x00000002U 1125 #define UART_DMACTL_TXDMAE_M 0x00000002U 1126 #define UART_DMACTL_TXDMAE_S 1U 1127 1128 // Field: [0] RXDMAE 1129 // 1130 // Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is 1131 // enabled. 1132 #define UART_DMACTL_RXDMAE 0x00000001U 1133 #define UART_DMACTL_RXDMAE_M 0x00000001U 1134 #define UART_DMACTL_RXDMAE_S 0U 1135 1136 1137 #endif // __UART__ 1138
