1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_UART_H__ 35 #define __HW_UART_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the UART register offsets. 40 // 41 //***************************************************************************** 42 #define UART_O_DR 0x00000000 43 #define UART_O_RSR 0x00000004 44 #define UART_O_ECR 0x00000004 45 #define UART_O_FR 0x00000018 46 #define UART_O_ILPR 0x00000020 47 #define UART_O_IBRD 0x00000024 48 #define UART_O_FBRD 0x00000028 49 #define UART_O_LCRH 0x0000002C 50 #define UART_O_CTL 0x00000030 51 #define UART_O_IFLS 0x00000034 52 #define UART_O_IM 0x00000038 53 #define UART_O_RIS 0x0000003C 54 #define UART_O_MIS 0x00000040 55 #define UART_O_ICR 0x00000044 56 #define UART_O_DMACTL 0x00000048 57 #define UART_O_LCTL 0x00000090 58 #define UART_O_LSS 0x00000094 59 #define UART_O_LTIM 0x00000098 60 #define UART_O_9BITADDR 0x000000A4 61 #define UART_O_9BITAMASK 0x000000A8 62 #define UART_O_PP 0x00000FC0 63 #define UART_O_CC 0x00000FC8 64 65 66 67 //****************************************************************************** 68 // 69 // The following are defines for the bit fields in the UART_O_DR register. 70 // 71 //****************************************************************************** 72 #define UART_DR_OE 0x00000800 // UART Overrun Error 73 #define UART_DR_BE 0x00000400 // UART Break Error 74 #define UART_DR_PE 0x00000200 // UART Parity Error 75 #define UART_DR_FE 0x00000100 // UART Framing Error 76 #define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received 77 #define UART_DR_DATA_S 0 78 //****************************************************************************** 79 // 80 // The following are defines for the bit fields in the UART_O_RSR register. 81 // 82 //****************************************************************************** 83 #define UART_RSR_OE 0x00000008 // UART Overrun Error 84 #define UART_RSR_BE 0x00000004 // UART Break Error 85 #define UART_RSR_PE 0x00000002 // UART Parity Error 86 #define UART_RSR_FE 0x00000001 // UART Framing Error 87 //****************************************************************************** 88 // 89 // The following are defines for the bit fields in the UART_O_ECR register. 90 // 91 //****************************************************************************** 92 #define UART_ECR_DATA_M 0x000000FF // Error Clear 93 #define UART_ECR_DATA_S 0 94 //****************************************************************************** 95 // 96 // The following are defines for the bit fields in the UART_O_FR register. 97 // 98 //****************************************************************************** 99 #define UART_FR_RI 0x00000100 // Ring Indicator 100 #define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty 101 #define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full 102 #define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full 103 #define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty 104 #define UART_FR_BUSY 0x00000008 // UART Busy 105 #define UART_FR_DCD 0x00000004 // Data Carrier Detect 106 #define UART_FR_DSR 0x00000002 // Data Set Ready 107 #define UART_FR_CTS 0x00000001 // Clear To Send 108 //****************************************************************************** 109 // 110 // The following are defines for the bit fields in the UART_O_ILPR register. 111 // 112 //****************************************************************************** 113 #define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor 114 #define UART_ILPR_ILPDVSR_S 0 115 //****************************************************************************** 116 // 117 // The following are defines for the bit fields in the UART_O_IBRD register. 118 // 119 //****************************************************************************** 120 #define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor 121 #define UART_IBRD_DIVINT_S 0 122 //****************************************************************************** 123 // 124 // The following are defines for the bit fields in the UART_O_FBRD register. 125 // 126 //****************************************************************************** 127 #define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor 128 #define UART_FBRD_DIVFRAC_S 0 129 //****************************************************************************** 130 // 131 // The following are defines for the bit fields in the UART_O_LCRH register. 132 // 133 //****************************************************************************** 134 #define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select 135 #define UART_LCRH_WLEN_M 0x00000060 // UART Word Length 0x00000000 : 136 // UART_LCRH_WLEN_5 : 5 bits 137 // (default) 0x00000020 : 138 // UART_LCRH_WLEN_6 : 6 bits 139 // 0x00000040 : UART_LCRH_WLEN_7 : 7 140 // bits 0x00000060 : 141 // UART_LCRH_WLEN_8 : 8 bits 142 #define UART_LCRH_WLEN_S 5 143 #define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs 144 #define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select 145 #define UART_LCRH_EPS 0x00000004 // UART Even Parity Select 146 #define UART_LCRH_PEN 0x00000002 // UART Parity Enable 147 #define UART_LCRH_BRK 0x00000001 // UART Send Break 148 #define UART_LCRH_WLEN_M 0x00000060 // UART Word Length 149 #define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) 150 #define UART_LCRH_WLEN_6 0x00000020 // 6 bits 151 #define UART_LCRH_WLEN_7 0x00000040 // 7 bits 152 #define UART_LCRH_WLEN_8 0x00000060 // 8 bits 153 //****************************************************************************** 154 // 155 // The following are defines for the bit fields in the UART_O_CTL register. 156 // 157 //****************************************************************************** 158 #define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send 159 #define UART_CTL_RTSEN 0x00004000 // Enable Request to Send 160 #define UART_CTL_RI 0x00002000 // Ring Indicator 161 #define UART_CTL_DCD 0x00001000 // Data Carrier Detect 162 #define UART_CTL_RTS 0x00000800 // Request to Send 163 #define UART_CTL_DTR 0x00000400 // Data Terminal Ready 164 #define UART_CTL_RXE 0x00000200 // UART Receive Enable 165 #define UART_CTL_TXE 0x00000100 // UART Transmit Enable 166 #define UART_CTL_LBE 0x00000080 // UART Loop Back Enable 167 #define UART_CTL_LIN 0x00000040 // LIN Mode Enable 168 #define UART_CTL_HSE 0x00000020 // High-Speed Enable 169 #define UART_CTL_EOT 0x00000010 // End of Transmission 170 #define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support 171 #define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode 172 #define UART_CTL_SIREN 0x00000002 // UART SIR Enable 173 #define UART_CTL_UARTEN 0x00000001 // UART Enable 174 //****************************************************************************** 175 // 176 // The following are defines for the bit fields in the UART_O_IFLS register. 177 // 178 //****************************************************************************** 179 #define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO 180 // Level Select 181 #define UART_IFLS_RX_S 3 182 #define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO 183 // Level Select 184 #define UART_IFLS_TX_S 0 185 //****************************************************************************** 186 // 187 // The following are defines for the bit fields in the UART_O_IM register. 188 // 189 //****************************************************************************** 190 #define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask 191 #define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask 192 #define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask 193 #define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask 194 #define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt 195 // Mask 196 #define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask 197 #define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt 198 // Mask 199 #define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt 200 // Mask 201 #define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask 202 #define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask 203 #define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt 204 // Mask 205 #define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt 206 // Mask 207 #define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask 208 #define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask 209 #define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem 210 // Interrupt Mask 211 #define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem 212 // Interrupt Mask 213 #define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem 214 // Interrupt Mask 215 #define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem 216 // Interrupt Mask 217 //****************************************************************************** 218 // 219 // The following are defines for the bit fields in the UART_O_RIS register. 220 // 221 //****************************************************************************** 222 #define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt 223 // Status 224 #define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status 225 #define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt 226 // Status 227 #define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt 228 // Status 229 #define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw 230 // Interrupt Status 231 #define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status 232 #define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw 233 // Interrupt Status 234 #define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt 235 // Status 236 #define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt 237 // Status 238 #define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt 239 // Status 240 #define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt 241 // Status 242 #define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw 243 // Interrupt Status 244 #define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt 245 // Status 246 #define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt 247 // Status 248 #define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw 249 // Interrupt Status 250 #define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem 251 // Raw Interrupt Status 252 #define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw 253 // Interrupt Status 254 #define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw 255 // Interrupt Status 256 //****************************************************************************** 257 // 258 // The following are defines for the bit fields in the UART_O_MIS register. 259 // 260 //****************************************************************************** 261 #define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt 262 // Status 263 #define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt 264 // Status 265 #define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt 266 // Status 267 #define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt 268 // Status 269 #define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked 270 // Interrupt Status 271 #define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt 272 // Status 273 #define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked 274 // Interrupt Status 275 #define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked 276 // Interrupt Status 277 #define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked 278 // Interrupt Status 279 #define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked 280 // Interrupt Status 281 #define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked 282 // Interrupt Status 283 #define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked 284 // Interrupt Status 285 #define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt 286 // Status 287 #define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt 288 // Status 289 #define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked 290 // Interrupt Status 291 #define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem 292 // Masked Interrupt Status 293 #define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked 294 // Interrupt Status 295 #define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked 296 // Interrupt Status 297 //****************************************************************************** 298 // 299 // The following are defines for the bit fields in the UART_O_ICR register. 300 // 301 //****************************************************************************** 302 #define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear 303 #define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear 304 #define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear 305 #define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear 306 #define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt 307 // Clear 308 #define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear 309 #define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt 310 // Clear 311 #define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear 312 #define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear 313 #define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear 314 #define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear 315 #define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear 316 #define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear 317 #define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear 318 #define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem 319 // Interrupt Clear 320 #define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem 321 // Interrupt Clear 322 #define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem 323 // Interrupt Clear 324 #define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem 325 // Interrupt Clear 326 //****************************************************************************** 327 // 328 // The following are defines for the bit fields in the UART_O_DMACTL register. 329 // 330 //****************************************************************************** 331 #define UART_DMACTL_DMAERR 0x00000004 // DMA on Error 332 #define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable 333 #define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable 334 //****************************************************************************** 335 // 336 // The following are defines for the bit fields in the UART_O_LCTL register. 337 // 338 //****************************************************************************** 339 #define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length 0x00000000 : 340 // UART_LCTL_BLEN_13T : Sync break 341 // length is 13T bits (default) 342 // 0x00000010 : UART_LCTL_BLEN_14T : 343 // Sync break length is 14T bits 344 // 0x00000020 : UART_LCTL_BLEN_15T : 345 // Sync break length is 15T bits 346 // 0x00000030 : UART_LCTL_BLEN_16T : 347 // Sync break length is 16T bits 348 #define UART_LCTL_BLEN_S 4 349 #define UART_LCTL_MASTER 0x00000001 // LIN Master Enable 350 //****************************************************************************** 351 // 352 // The following are defines for the bit fields in the UART_O_LSS register. 353 // 354 //****************************************************************************** 355 #define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot 356 #define UART_LSS_TSS_S 0 357 //****************************************************************************** 358 // 359 // The following are defines for the bit fields in the UART_O_LTIM register. 360 // 361 //****************************************************************************** 362 #define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value 363 #define UART_LTIM_TIMER_S 0 364 //****************************************************************************** 365 // 366 // The following are defines for the bit fields in the 367 // UART_O_9BITADDR register. 368 // 369 //****************************************************************************** 370 #define UART_9BITADDR_9BITEN \ 371 0x00008000 // Enable 9-Bit Mode 372 373 #define UART_9BITADDR_ADDR_M \ 374 0x000000FF // Self Address for 9-Bit Mode 375 376 #define UART_9BITADDR_ADDR_S 0 377 //****************************************************************************** 378 // 379 // The following are defines for the bit fields in the 380 // UART_O_9BITAMASK register. 381 // 382 //****************************************************************************** 383 #define UART_9BITAMASK_RANGE_M \ 384 0x0000FF00 // Self Address Range for 9-Bit 385 // Mode 386 387 #define UART_9BITAMASK_RANGE_S 8 388 #define UART_9BITAMASK_MASK_M \ 389 0x000000FF // Self Address Mask for 9-Bit Mode 390 391 #define UART_9BITAMASK_MASK_S 0 392 //****************************************************************************** 393 // 394 // The following are defines for the bit fields in the UART_O_PP register. 395 // 396 //****************************************************************************** 397 #define UART_PP_MSE 0x00000008 // Modem Support Extended 398 #define UART_PP_MS 0x00000004 // Modem Support 399 #define UART_PP_NB 0x00000002 // 9-Bit Support 400 #define UART_PP_SC 0x00000001 // Smart Card Support 401 //****************************************************************************** 402 // 403 // The following are defines for the bit fields in the UART_O_CC register. 404 // 405 //****************************************************************************** 406 #define UART_CC_CS_M 0x0000000F // UART Baud Clock Source 407 // 0x00000005 : UART_CC_CS_PIOSC : 408 // PIOSC 0x00000000 : 409 // UART_CC_CS_SYSCLK : The system 410 // clock (default) 411 #define UART_CC_CS_S 0 412 413 414 415 #endif // __HW_UART_H__ 416
