1 /****************************************************************************** 2 * Filename: hw_systim_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_SYSTIM_H__ 34 #define __HW_SYSTIM_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // SYSTIM component 40 // 41 //***************************************************************************** 42 // Module Description 43 #define SYSTIM_O_DESC 0x00000000U 44 45 // Interrupt mask 46 #define SYSTIM_O_IMASK 0x00000044U 47 48 // Raw interrupt status 49 #define SYSTIM_O_RIS 0x00000048U 50 51 // Masked interrupt status 52 #define SYSTIM_O_MIS 0x0000004CU 53 54 // Interrupt set 55 #define SYSTIM_O_ISET 0x00000050U 56 57 // Interrupt clear 58 #define SYSTIM_O_ICLR 0x00000054U 59 60 // Interrupt mask set 61 #define SYSTIM_O_IMSET 0x00000058U 62 63 // Interrupt mask clear 64 #define SYSTIM_O_IMCLR 0x0000005CU 65 66 // Emulation 67 #define SYSTIM_O_EMU 0x00000060U 68 69 // Systime Count Value [31:0] 70 #define SYSTIM_O_TIME250N 0x00000100U 71 72 // Systime Count Value [33:2] 73 #define SYSTIM_O_TIME1U 0x00000104U 74 75 // channel's Ouput Value 76 #define SYSTIM_O_OUT 0x00000108U 77 78 // channel0 Configuration. 79 #define SYSTIM_O_CH0CFG 0x0000010CU 80 81 // channel1 Configuration. 82 #define SYSTIM_O_CH1CFG 0x00000110U 83 84 // channel2 Configuration. 85 #define SYSTIM_O_CH2CFG 0x00000114U 86 87 // channel3 Configuration. 88 #define SYSTIM_O_CH3CFG 0x00000118U 89 90 // channel4 Configuration. 91 #define SYSTIM_O_CH4CFG 0x0000011CU 92 93 // Channel 0 Capture/Compare Value 94 #define SYSTIM_O_CH0CC 0x00000120U 95 96 // Channel 1 Capture/Compare Value 97 #define SYSTIM_O_CH1CC 0x00000124U 98 99 // Channel 2 Capture/Compare Value 100 #define SYSTIM_O_CH2CC 0x00000128U 101 102 // Channel 3 Capture/Compare Value 103 #define SYSTIM_O_CH3CC 0x0000012CU 104 105 // Channel 4 Capture/Compare Value 106 #define SYSTIM_O_CH4CC 0x00000130U 107 108 // Systimer's Time bit 109 #define SYSTIM_O_TIMEBIT 0x00000134U 110 111 // Timer Status 112 #define SYSTIM_O_STATUS 0x00000140U 113 114 // Channel arming set 115 #define SYSTIM_O_ARMSET 0x00000144U 116 117 // Channel Arming clear 118 #define SYSTIM_O_ARMCLR 0x00000148U 119 120 // Channel 0 Save/Restore Value 121 #define SYSTIM_O_CH0CCSR 0x0000014CU 122 123 // Channel 1 Save/Restore Value 124 #define SYSTIM_O_CH1CCSR 0x00000150U 125 126 // Channel 2 Save/Restore Value 127 #define SYSTIM_O_CH2CCSR 0x00000154U 128 129 // Channel 3 Save/Restore Value 130 #define SYSTIM_O_CH3CCSR 0x00000158U 131 132 // Channel 4 Save/Restore Value 133 #define SYSTIM_O_CH4CCSR 0x0000015CU 134 135 //***************************************************************************** 136 // 137 // Register: SYSTIM_O_DESC 138 // 139 //***************************************************************************** 140 // Field: [31:16] MODID 141 // 142 // Module identifier used to uniquely identify this IP. 143 #define SYSTIM_DESC_MODID_W 16U 144 #define SYSTIM_DESC_MODID_M 0xFFFF0000U 145 #define SYSTIM_DESC_MODID_S 16U 146 147 // Field: [15:12] STDIPOFF 148 // 149 // Standard IP MMR block offset. Standard IP MMRs are the set of from 150 // aggregated IRQ registers till DTB. 151 // 152 // 0: Standard IP MMRs do not exist 153 // 154 // 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP 155 // address) 156 #define SYSTIM_DESC_STDIPOFF_W 4U 157 #define SYSTIM_DESC_STDIPOFF_M 0x0000F000U 158 #define SYSTIM_DESC_STDIPOFF_S 12U 159 160 // Field: [11:8] INSTIDX 161 // 162 // IP Instance ID number. If multiple instances of IP exists in SOC, this field 163 // can identify the instance number 0-15 164 #define SYSTIM_DESC_INSTIDX_W 4U 165 #define SYSTIM_DESC_INSTIDX_M 0x00000F00U 166 #define SYSTIM_DESC_INSTIDX_S 8U 167 168 // Field: [7:4] MAJREV 169 // 170 // Major revision of IP 0-15 171 #define SYSTIM_DESC_MAJREV_W 4U 172 #define SYSTIM_DESC_MAJREV_M 0x000000F0U 173 #define SYSTIM_DESC_MAJREV_S 4U 174 175 // Field: [3:0] MINREV 176 // 177 // Minor revision of IP 0-15. 178 #define SYSTIM_DESC_MINREV_W 4U 179 #define SYSTIM_DESC_MINREV_M 0x0000000FU 180 #define SYSTIM_DESC_MINREV_S 0U 181 182 //***************************************************************************** 183 // 184 // Register: SYSTIM_O_IMASK 185 // 186 //***************************************************************************** 187 // Field: [5] OVFL 188 // 189 // Systimer counter overflow event interrupt mask. 190 // ENUMs: 191 // EN Enable Interrrupt Mask 192 // DIS Disable Interrupt Mask 193 #define SYSTIM_IMASK_OVFL 0x00000020U 194 #define SYSTIM_IMASK_OVFL_M 0x00000020U 195 #define SYSTIM_IMASK_OVFL_S 5U 196 #define SYSTIM_IMASK_OVFL_EN 0x00000020U 197 #define SYSTIM_IMASK_OVFL_DIS 0x00000000U 198 199 // Field: [4] EV4 200 // 201 // Systimer channel 4 event interrupt mask. 202 // ENUMs: 203 // EN Enable Interrrupt Mask 204 // DIS Disable Interrupt Mask 205 #define SYSTIM_IMASK_EV4 0x00000010U 206 #define SYSTIM_IMASK_EV4_M 0x00000010U 207 #define SYSTIM_IMASK_EV4_S 4U 208 #define SYSTIM_IMASK_EV4_EN 0x00000010U 209 #define SYSTIM_IMASK_EV4_DIS 0x00000000U 210 211 // Field: [3] EV3 212 // 213 // Systimer channel 3 event interrupt mask. 214 // ENUMs: 215 // EN Enable Interrrupt Mask 216 // DIS Disable Interrupt Mask 217 #define SYSTIM_IMASK_EV3 0x00000008U 218 #define SYSTIM_IMASK_EV3_M 0x00000008U 219 #define SYSTIM_IMASK_EV3_S 3U 220 #define SYSTIM_IMASK_EV3_EN 0x00000008U 221 #define SYSTIM_IMASK_EV3_DIS 0x00000000U 222 223 // Field: [2] EV2 224 // 225 // Systimer channel 2 event interrupt mask. 226 // ENUMs: 227 // EN Enable Interrrupt Mask 228 // DIS Disable Interrupt Mask 229 #define SYSTIM_IMASK_EV2 0x00000004U 230 #define SYSTIM_IMASK_EV2_M 0x00000004U 231 #define SYSTIM_IMASK_EV2_S 2U 232 #define SYSTIM_IMASK_EV2_EN 0x00000004U 233 #define SYSTIM_IMASK_EV2_DIS 0x00000000U 234 235 // Field: [1] EV1 236 // 237 // Systimer channel 1 event interrupt mask. 238 // ENUMs: 239 // EN Enable Interrrupt Mask 240 // DIS Disable Interrupt Mask 241 #define SYSTIM_IMASK_EV1 0x00000002U 242 #define SYSTIM_IMASK_EV1_M 0x00000002U 243 #define SYSTIM_IMASK_EV1_S 1U 244 #define SYSTIM_IMASK_EV1_EN 0x00000002U 245 #define SYSTIM_IMASK_EV1_DIS 0x00000000U 246 247 // Field: [0] EV0 248 // 249 // Systimer channel 0 event interrupt mask. 250 // ENUMs: 251 // EN Enable Interrrupt Mask 252 // DIS Disable Interrupt Mask 253 #define SYSTIM_IMASK_EV0 0x00000001U 254 #define SYSTIM_IMASK_EV0_M 0x00000001U 255 #define SYSTIM_IMASK_EV0_S 0U 256 #define SYSTIM_IMASK_EV0_EN 0x00000001U 257 #define SYSTIM_IMASK_EV0_DIS 0x00000000U 258 259 //***************************************************************************** 260 // 261 // Register: SYSTIM_O_RIS 262 // 263 //***************************************************************************** 264 // Field: [5] OVFL 265 // 266 // Raw interrupt status for Systimer counter overflow event. 267 // This bit is set to 1 when an event is received on SysTimer Overflow occurs. 268 // ENUMs: 269 // SET Interrupt occured 270 // CLR Interrupt did not occur 271 #define SYSTIM_RIS_OVFL 0x00000020U 272 #define SYSTIM_RIS_OVFL_M 0x00000020U 273 #define SYSTIM_RIS_OVFL_S 5U 274 #define SYSTIM_RIS_OVFL_SET 0x00000020U 275 #define SYSTIM_RIS_OVFL_CLR 0x00000000U 276 277 // Field: [4] EV4 278 // 279 // Raw interrupt status for channel 4 event. 280 // This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 281 // 4. 282 // ENUMs: 283 // SET Interrupt occured 284 // CLR Interrupt did not occur 285 #define SYSTIM_RIS_EV4 0x00000010U 286 #define SYSTIM_RIS_EV4_M 0x00000010U 287 #define SYSTIM_RIS_EV4_S 4U 288 #define SYSTIM_RIS_EV4_SET 0x00000010U 289 #define SYSTIM_RIS_EV4_CLR 0x00000000U 290 291 // Field: [3] EV3 292 // 293 // Raw interrupt status for channel 3 event. 294 // This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 295 // 3. 296 // ENUMs: 297 // SET Interrupt occured 298 // CLR Interrupt did not occur 299 #define SYSTIM_RIS_EV3 0x00000008U 300 #define SYSTIM_RIS_EV3_M 0x00000008U 301 #define SYSTIM_RIS_EV3_S 3U 302 #define SYSTIM_RIS_EV3_SET 0x00000008U 303 #define SYSTIM_RIS_EV3_CLR 0x00000000U 304 305 // Field: [2] EV2 306 // 307 // Raw interrupt status for channel 2 Event. 308 // This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 309 // 2. 310 // ENUMs: 311 // SET Interrupt occured 312 // CLR Interrupt did not occur 313 #define SYSTIM_RIS_EV2 0x00000004U 314 #define SYSTIM_RIS_EV2_M 0x00000004U 315 #define SYSTIM_RIS_EV2_S 2U 316 #define SYSTIM_RIS_EV2_SET 0x00000004U 317 #define SYSTIM_RIS_EV2_CLR 0x00000000U 318 319 // Field: [1] EV1 320 // 321 // Raw interrupt status for channel 1 event. 322 // This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 323 // 1. 324 // ENUMs: 325 // SET Interrupt occured 326 // CLR Interrupt did not occur 327 #define SYSTIM_RIS_EV1 0x00000002U 328 #define SYSTIM_RIS_EV1_M 0x00000002U 329 #define SYSTIM_RIS_EV1_S 1U 330 #define SYSTIM_RIS_EV1_SET 0x00000002U 331 #define SYSTIM_RIS_EV1_CLR 0x00000000U 332 333 // Field: [0] EV0 334 // 335 // Raw interrupt status for channel 0 event. 336 // This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 337 // 0. 338 // ENUMs: 339 // SET Interrupt occured 340 // CLR Interrupt did not occur 341 #define SYSTIM_RIS_EV0 0x00000001U 342 #define SYSTIM_RIS_EV0_M 0x00000001U 343 #define SYSTIM_RIS_EV0_S 0U 344 #define SYSTIM_RIS_EV0_SET 0x00000001U 345 #define SYSTIM_RIS_EV0_CLR 0x00000000U 346 347 //***************************************************************************** 348 // 349 // Register: SYSTIM_O_MIS 350 // 351 //***************************************************************************** 352 // Field: [5] OVFL 353 // 354 // Mask Interrupt status for Systimer counter overflow Event in MIS register. 355 // ENUMs: 356 // SET Interrupt occured 357 // CLR Interrupt did not occur 358 #define SYSTIM_MIS_OVFL 0x00000020U 359 #define SYSTIM_MIS_OVFL_M 0x00000020U 360 #define SYSTIM_MIS_OVFL_S 5U 361 #define SYSTIM_MIS_OVFL_SET 0x00000020U 362 #define SYSTIM_MIS_OVFL_CLR 0x00000000U 363 364 // Field: [4] EV4 365 // 366 // Mask interrupt status for channel 4 event. 367 // ENUMs: 368 // SET Interrupt occured 369 // CLR Interrupt did not occur 370 #define SYSTIM_MIS_EV4 0x00000010U 371 #define SYSTIM_MIS_EV4_M 0x00000010U 372 #define SYSTIM_MIS_EV4_S 4U 373 #define SYSTIM_MIS_EV4_SET 0x00000010U 374 #define SYSTIM_MIS_EV4_CLR 0x00000000U 375 376 // Field: [3] EV3 377 // 378 // Mask interrupt status for channel 3 event. 379 // ENUMs: 380 // SET Interrupt occured 381 // CLR Interrupt did not occur 382 #define SYSTIM_MIS_EV3 0x00000008U 383 #define SYSTIM_MIS_EV3_M 0x00000008U 384 #define SYSTIM_MIS_EV3_S 3U 385 #define SYSTIM_MIS_EV3_SET 0x00000008U 386 #define SYSTIM_MIS_EV3_CLR 0x00000000U 387 388 // Field: [2] EV2 389 // 390 // Mask interrupt status for channel 2 event. 391 // ENUMs: 392 // SET Interrupt occured 393 // CLR Interrupt did not occur 394 #define SYSTIM_MIS_EV2 0x00000004U 395 #define SYSTIM_MIS_EV2_M 0x00000004U 396 #define SYSTIM_MIS_EV2_S 2U 397 #define SYSTIM_MIS_EV2_SET 0x00000004U 398 #define SYSTIM_MIS_EV2_CLR 0x00000000U 399 400 // Field: [1] EV1 401 // 402 // Mask interrupt status for channel 1 event. 403 // ENUMs: 404 // SET Interrupt occured 405 // CLR Interrupt did not occur 406 #define SYSTIM_MIS_EV1 0x00000002U 407 #define SYSTIM_MIS_EV1_M 0x00000002U 408 #define SYSTIM_MIS_EV1_S 1U 409 #define SYSTIM_MIS_EV1_SET 0x00000002U 410 #define SYSTIM_MIS_EV1_CLR 0x00000000U 411 412 // Field: [0] EV0 413 // 414 // Mask interrupt status for channel 0 event. 415 // ENUMs: 416 // SET Interrupt occured 417 // CLR Interrupt did not occur 418 #define SYSTIM_MIS_EV0 0x00000001U 419 #define SYSTIM_MIS_EV0_M 0x00000001U 420 #define SYSTIM_MIS_EV0_S 0U 421 #define SYSTIM_MIS_EV0_SET 0x00000001U 422 #define SYSTIM_MIS_EV0_CLR 0x00000000U 423 424 //***************************************************************************** 425 // 426 // Register: SYSTIM_O_ISET 427 // 428 //***************************************************************************** 429 // Field: [5] OVFL 430 // 431 // Sets Systimer counter overflow interrupt. 432 // ENUMs: 433 // SET Set Interrupt 434 // NOEFF Writing 0 has no effect 435 #define SYSTIM_ISET_OVFL 0x00000020U 436 #define SYSTIM_ISET_OVFL_M 0x00000020U 437 #define SYSTIM_ISET_OVFL_S 5U 438 #define SYSTIM_ISET_OVFL_SET 0x00000020U 439 #define SYSTIM_ISET_OVFL_NOEFF 0x00000000U 440 441 // Field: [4] EV4 442 // 443 // Sets channel 4 interrupt. 444 // ENUMs: 445 // SET Set Interrupt 446 // NOEFF Writing 0 has no effect 447 #define SYSTIM_ISET_EV4 0x00000010U 448 #define SYSTIM_ISET_EV4_M 0x00000010U 449 #define SYSTIM_ISET_EV4_S 4U 450 #define SYSTIM_ISET_EV4_SET 0x00000010U 451 #define SYSTIM_ISET_EV4_NOEFF 0x00000000U 452 453 // Field: [3] EV3 454 // 455 // Sets channel 3 interrupt. 456 // ENUMs: 457 // SET Set Interrupt 458 // NOEFF Writing 0 has no effect 459 #define SYSTIM_ISET_EV3 0x00000008U 460 #define SYSTIM_ISET_EV3_M 0x00000008U 461 #define SYSTIM_ISET_EV3_S 3U 462 #define SYSTIM_ISET_EV3_SET 0x00000008U 463 #define SYSTIM_ISET_EV3_NOEFF 0x00000000U 464 465 // Field: [2] EV2 466 // 467 // Sets channel 2 interrupt. 468 // ENUMs: 469 // SET Set Interrupt 470 // NOEFF Writing 0 has no effect 471 #define SYSTIM_ISET_EV2 0x00000004U 472 #define SYSTIM_ISET_EV2_M 0x00000004U 473 #define SYSTIM_ISET_EV2_S 2U 474 #define SYSTIM_ISET_EV2_SET 0x00000004U 475 #define SYSTIM_ISET_EV2_NOEFF 0x00000000U 476 477 // Field: [1] EV1 478 // 479 // Sets channel 1 interrupt. 480 // ENUMs: 481 // SET Set Interrupt 482 // NOEFF Writing 0 has no effect 483 #define SYSTIM_ISET_EV1 0x00000002U 484 #define SYSTIM_ISET_EV1_M 0x00000002U 485 #define SYSTIM_ISET_EV1_S 1U 486 #define SYSTIM_ISET_EV1_SET 0x00000002U 487 #define SYSTIM_ISET_EV1_NOEFF 0x00000000U 488 489 // Field: [0] EV0 490 // 491 // Sets channel 0 interrupt. 492 // ENUMs: 493 // SET Set Interrupt 494 // NOEFF Writing 0 has no effect 495 #define SYSTIM_ISET_EV0 0x00000001U 496 #define SYSTIM_ISET_EV0_M 0x00000001U 497 #define SYSTIM_ISET_EV0_S 0U 498 #define SYSTIM_ISET_EV0_SET 0x00000001U 499 #define SYSTIM_ISET_EV0_NOEFF 0x00000000U 500 501 //***************************************************************************** 502 // 503 // Register: SYSTIM_O_ICLR 504 // 505 //***************************************************************************** 506 // Field: [5] OVFL 507 // 508 // Clears Systimer counter overflow interrupt. 509 // ENUMs: 510 // CLR Clear Interrupt 511 // NOEFF Writing 0 has no effect 512 #define SYSTIM_ICLR_OVFL 0x00000020U 513 #define SYSTIM_ICLR_OVFL_M 0x00000020U 514 #define SYSTIM_ICLR_OVFL_S 5U 515 #define SYSTIM_ICLR_OVFL_CLR 0x00000020U 516 #define SYSTIM_ICLR_OVFL_NOEFF 0x00000000U 517 518 // Field: [4] EV4 519 // 520 // Clears channel 4 interrupt. 521 // ENUMs: 522 // CLR Clear Interrupt 523 // NOEFF Writing 0 has no effect 524 #define SYSTIM_ICLR_EV4 0x00000010U 525 #define SYSTIM_ICLR_EV4_M 0x00000010U 526 #define SYSTIM_ICLR_EV4_S 4U 527 #define SYSTIM_ICLR_EV4_CLR 0x00000010U 528 #define SYSTIM_ICLR_EV4_NOEFF 0x00000000U 529 530 // Field: [3] EV3 531 // 532 // Clears channel 3 interrupt. 533 // ENUMs: 534 // CLR Clear Interrupt 535 // NOEFF Writing 0 has no effect 536 #define SYSTIM_ICLR_EV3 0x00000008U 537 #define SYSTIM_ICLR_EV3_M 0x00000008U 538 #define SYSTIM_ICLR_EV3_S 3U 539 #define SYSTIM_ICLR_EV3_CLR 0x00000008U 540 #define SYSTIM_ICLR_EV3_NOEFF 0x00000000U 541 542 // Field: [2] EV2 543 // 544 // Clears channel 2 interrupt. 545 // ENUMs: 546 // CLR Clear Interrupt 547 // NOEFF Writing 0 has no effect 548 #define SYSTIM_ICLR_EV2 0x00000004U 549 #define SYSTIM_ICLR_EV2_M 0x00000004U 550 #define SYSTIM_ICLR_EV2_S 2U 551 #define SYSTIM_ICLR_EV2_CLR 0x00000004U 552 #define SYSTIM_ICLR_EV2_NOEFF 0x00000000U 553 554 // Field: [1] EV1 555 // 556 // Clears channel 1 interrupt. 557 // ENUMs: 558 // CLR Clear Interrupt 559 // NOEFF Writing 0 has no effect 560 #define SYSTIM_ICLR_EV1 0x00000002U 561 #define SYSTIM_ICLR_EV1_M 0x00000002U 562 #define SYSTIM_ICLR_EV1_S 1U 563 #define SYSTIM_ICLR_EV1_CLR 0x00000002U 564 #define SYSTIM_ICLR_EV1_NOEFF 0x00000000U 565 566 // Field: [0] EV0 567 // 568 // Clears channel 0 interrupt. 569 // ENUMs: 570 // CLR Clear Interrupt 571 // NOEFF Writing 0 has no effect 572 #define SYSTIM_ICLR_EV0 0x00000001U 573 #define SYSTIM_ICLR_EV0_M 0x00000001U 574 #define SYSTIM_ICLR_EV0_S 0U 575 #define SYSTIM_ICLR_EV0_CLR 0x00000001U 576 #define SYSTIM_ICLR_EV0_NOEFF 0x00000000U 577 578 //***************************************************************************** 579 // 580 // Register: SYSTIM_O_IMSET 581 // 582 //***************************************************************************** 583 // Field: [5] OVFL 584 // 585 // Sets Timer Overflow Event Interrupt Mask. 586 // ENUMs: 587 // SET Set interrupt mask 588 // NOEFF Writing 0 has no effect 589 #define SYSTIM_IMSET_OVFL 0x00000020U 590 #define SYSTIM_IMSET_OVFL_M 0x00000020U 591 #define SYSTIM_IMSET_OVFL_S 5U 592 #define SYSTIM_IMSET_OVFL_SET 0x00000020U 593 #define SYSTIM_IMSET_OVFL_NOEFF 0x00000000U 594 595 // Field: [4] EV4 596 // 597 // Sets channel4 Event Interrupt mask 598 // ENUMs: 599 // SET Set interrupt mask 600 // NOEFF Writing 0 has no effect 601 #define SYSTIM_IMSET_EV4 0x00000010U 602 #define SYSTIM_IMSET_EV4_M 0x00000010U 603 #define SYSTIM_IMSET_EV4_S 4U 604 #define SYSTIM_IMSET_EV4_SET 0x00000010U 605 #define SYSTIM_IMSET_EV4_NOEFF 0x00000000U 606 607 // Field: [3] EV3 608 // 609 // Sets channel3 Event Interrupt mask 610 // ENUMs: 611 // SET Set interrupt mask 612 // NOEFF Writing 0 has no effect 613 #define SYSTIM_IMSET_EV3 0x00000008U 614 #define SYSTIM_IMSET_EV3_M 0x00000008U 615 #define SYSTIM_IMSET_EV3_S 3U 616 #define SYSTIM_IMSET_EV3_SET 0x00000008U 617 #define SYSTIM_IMSET_EV3_NOEFF 0x00000000U 618 619 // Field: [2] EV2 620 // 621 // Sets channel2 Event Interrupt mask 622 // ENUMs: 623 // SET Set interrupt mask 624 // NOEFF Writing 0 has no effect 625 #define SYSTIM_IMSET_EV2 0x00000004U 626 #define SYSTIM_IMSET_EV2_M 0x00000004U 627 #define SYSTIM_IMSET_EV2_S 2U 628 #define SYSTIM_IMSET_EV2_SET 0x00000004U 629 #define SYSTIM_IMSET_EV2_NOEFF 0x00000000U 630 631 // Field: [1] EV1 632 // 633 // Sets channel1 Event Interrupt mask 634 // ENUMs: 635 // SET Set interrupt mask 636 // NOEFF Writing 0 has no effect 637 #define SYSTIM_IMSET_EV1 0x00000002U 638 #define SYSTIM_IMSET_EV1_M 0x00000002U 639 #define SYSTIM_IMSET_EV1_S 1U 640 #define SYSTIM_IMSET_EV1_SET 0x00000002U 641 #define SYSTIM_IMSET_EV1_NOEFF 0x00000000U 642 643 // Field: [0] EV0 644 // 645 // Sets channel0 Event Interrupt mask 646 // ENUMs: 647 // SET Set interrupt mask 648 // NOEFF Writing 0 has no effect 649 #define SYSTIM_IMSET_EV0 0x00000001U 650 #define SYSTIM_IMSET_EV0_M 0x00000001U 651 #define SYSTIM_IMSET_EV0_S 0U 652 #define SYSTIM_IMSET_EV0_SET 0x00000001U 653 #define SYSTIM_IMSET_EV0_NOEFF 0x00000000U 654 655 //***************************************************************************** 656 // 657 // Register: SYSTIM_O_IMCLR 658 // 659 //***************************************************************************** 660 // Field: [5] OVFL 661 // 662 // Clears Timer Overflow Event Interrupt Mask. 663 // ENUMs: 664 // CLR Clear interrupt mask 665 // NOEFF Writing 0 has no effect 666 #define SYSTIM_IMCLR_OVFL 0x00000020U 667 #define SYSTIM_IMCLR_OVFL_M 0x00000020U 668 #define SYSTIM_IMCLR_OVFL_S 5U 669 #define SYSTIM_IMCLR_OVFL_CLR 0x00000020U 670 #define SYSTIM_IMCLR_OVFL_NOEFF 0x00000000U 671 672 // Field: [4] EV4 673 // 674 // Clears channel4 Event Interrupt Mask. 675 // ENUMs: 676 // CLR Clear interrupt mask 677 // NOEFF Writing 0 has no effect 678 #define SYSTIM_IMCLR_EV4 0x00000010U 679 #define SYSTIM_IMCLR_EV4_M 0x00000010U 680 #define SYSTIM_IMCLR_EV4_S 4U 681 #define SYSTIM_IMCLR_EV4_CLR 0x00000010U 682 #define SYSTIM_IMCLR_EV4_NOEFF 0x00000000U 683 684 // Field: [3] EV3 685 // 686 // Clears channel3 Event Interrupt Mask. 687 // ENUMs: 688 // CLR Clear interrupt mask 689 // NOEFF Writing 0 has no effect 690 #define SYSTIM_IMCLR_EV3 0x00000008U 691 #define SYSTIM_IMCLR_EV3_M 0x00000008U 692 #define SYSTIM_IMCLR_EV3_S 3U 693 #define SYSTIM_IMCLR_EV3_CLR 0x00000008U 694 #define SYSTIM_IMCLR_EV3_NOEFF 0x00000000U 695 696 // Field: [2] EV2 697 // 698 // Clears channel2 Event Interrupt Mask. 699 // ENUMs: 700 // CLR Clear interrupt mask 701 // NOEFF Writing 0 has no effect 702 #define SYSTIM_IMCLR_EV2 0x00000004U 703 #define SYSTIM_IMCLR_EV2_M 0x00000004U 704 #define SYSTIM_IMCLR_EV2_S 2U 705 #define SYSTIM_IMCLR_EV2_CLR 0x00000004U 706 #define SYSTIM_IMCLR_EV2_NOEFF 0x00000000U 707 708 // Field: [1] EV1 709 // 710 // Clears channel1 Event Interrupt Mask. 711 // ENUMs: 712 // CLR Clear interrupt mask 713 // NOEFF Writing 0 has no effect 714 #define SYSTIM_IMCLR_EV1 0x00000002U 715 #define SYSTIM_IMCLR_EV1_M 0x00000002U 716 #define SYSTIM_IMCLR_EV1_S 1U 717 #define SYSTIM_IMCLR_EV1_CLR 0x00000002U 718 #define SYSTIM_IMCLR_EV1_NOEFF 0x00000000U 719 720 // Field: [0] EV0 721 // 722 // Clears channel0 Event Interrupt Mask. 723 // ENUMs: 724 // CLR Clear interrupt mask 725 // NOEFF Writing 0 has no effect 726 #define SYSTIM_IMCLR_EV0 0x00000001U 727 #define SYSTIM_IMCLR_EV0_M 0x00000001U 728 #define SYSTIM_IMCLR_EV0_S 0U 729 #define SYSTIM_IMCLR_EV0_CLR 0x00000001U 730 #define SYSTIM_IMCLR_EV0_NOEFF 0x00000000U 731 732 //***************************************************************************** 733 // 734 // Register: SYSTIM_O_EMU 735 // 736 //***************************************************************************** 737 // Field: [0] HALT 738 // 739 // Halt control. 740 // ENUMs: 741 // STOP Freeze option. The IP freezes functionality when 742 // the core halted input is asserted, and resumes 743 // when it is deasserted. The freeze can either be 744 // immediate or after the IP has reached a 745 // boundary from where it can resume without 746 // corruption. 747 // RUN Free run option. The IP ignores the state of the 748 // core halted input. 749 #define SYSTIM_EMU_HALT 0x00000001U 750 #define SYSTIM_EMU_HALT_M 0x00000001U 751 #define SYSTIM_EMU_HALT_S 0U 752 #define SYSTIM_EMU_HALT_STOP 0x00000001U 753 #define SYSTIM_EMU_HALT_RUN 0x00000000U 754 755 //***************************************************************************** 756 // 757 // Register: SYSTIM_O_TIME250N 758 // 759 //***************************************************************************** 760 // Field: [31:0] VAL 761 // 762 // 32-bit counter value [31:0]. This will provide a 250ns resolution and a 763 // range of 17.9m. 764 #define SYSTIM_TIME250N_VAL_W 32U 765 #define SYSTIM_TIME250N_VAL_M 0xFFFFFFFFU 766 #define SYSTIM_TIME250N_VAL_S 0U 767 768 //***************************************************************************** 769 // 770 // Register: SYSTIM_O_TIME1U 771 // 772 //***************************************************************************** 773 // Field: [31:0] VAL 774 // 775 // 32-bit counter value [33:2]. This will provide a resolution of 1us and a 776 // range of 1hr and 11m. 777 #define SYSTIM_TIME1U_VAL_W 32U 778 #define SYSTIM_TIME1U_VAL_M 0xFFFFFFFFU 779 #define SYSTIM_TIME1U_VAL_S 0U 780 781 //***************************************************************************** 782 // 783 // Register: SYSTIM_O_OUT 784 // 785 //***************************************************************************** 786 // Field: [4] OUT4 787 // 788 // Output Value of channel 4. 789 // ENUMs: 790 // SET Event occured 791 // CLR Event did not occur. 792 #define SYSTIM_OUT_OUT4 0x00000010U 793 #define SYSTIM_OUT_OUT4_M 0x00000010U 794 #define SYSTIM_OUT_OUT4_S 4U 795 #define SYSTIM_OUT_OUT4_SET 0x00000010U 796 #define SYSTIM_OUT_OUT4_CLR 0x00000000U 797 798 // Field: [3] OUT3 799 // 800 // Output Value of channel 3. 801 // ENUMs: 802 // SET Event occured 803 // CLR Event did not occur. 804 #define SYSTIM_OUT_OUT3 0x00000008U 805 #define SYSTIM_OUT_OUT3_M 0x00000008U 806 #define SYSTIM_OUT_OUT3_S 3U 807 #define SYSTIM_OUT_OUT3_SET 0x00000008U 808 #define SYSTIM_OUT_OUT3_CLR 0x00000000U 809 810 // Field: [2] OUT2 811 // 812 // Output Value of channel 2. 813 // ENUMs: 814 // SET Event occured 815 // CLR Event did not occur. 816 #define SYSTIM_OUT_OUT2 0x00000004U 817 #define SYSTIM_OUT_OUT2_M 0x00000004U 818 #define SYSTIM_OUT_OUT2_S 2U 819 #define SYSTIM_OUT_OUT2_SET 0x00000004U 820 #define SYSTIM_OUT_OUT2_CLR 0x00000000U 821 822 // Field: [1] OUT1 823 // 824 // Output Value of channel 1. 825 // ENUMs: 826 // SET Event occured 827 // CLR Event did not occur. 828 #define SYSTIM_OUT_OUT1 0x00000002U 829 #define SYSTIM_OUT_OUT1_M 0x00000002U 830 #define SYSTIM_OUT_OUT1_S 1U 831 #define SYSTIM_OUT_OUT1_SET 0x00000002U 832 #define SYSTIM_OUT_OUT1_CLR 0x00000000U 833 834 // Field: [0] OUT0 835 // 836 // Output Value of channel 0. 837 // ENUMs: 838 // SET Event occured 839 // CLR Event did not occur. 840 #define SYSTIM_OUT_OUT0 0x00000001U 841 #define SYSTIM_OUT_OUT0_M 0x00000001U 842 #define SYSTIM_OUT_OUT0_S 0U 843 #define SYSTIM_OUT_OUT0_SET 0x00000001U 844 #define SYSTIM_OUT_OUT0_CLR 0x00000000U 845 846 //***************************************************************************** 847 // 848 // Register: SYSTIM_O_CH0CFG 849 // 850 //***************************************************************************** 851 // Field: [4] RES 852 // 853 // This bit decides the RESOLUTION of the channel that will be used. 854 // ENUMs: 855 // NS channel Works in Timer's 250ns resolution 856 // US channel Works in Timer's 1us Resolution. 857 #define SYSTIM_CH0CFG_RES 0x00000010U 858 #define SYSTIM_CH0CFG_RES_M 0x00000010U 859 #define SYSTIM_CH0CFG_RES_S 4U 860 #define SYSTIM_CH0CFG_RES_NS 0x00000010U 861 #define SYSTIM_CH0CFG_RES_US 0x00000000U 862 863 // Field: [3] REARM 864 // 865 // When Rearm is enabled the channel remains in continous capture mode. 866 // Otherwise it'll be in one shot capture mode. Rearm is only valid for capture 867 // mode. 868 // ENUMs: 869 // EN Re arm is enabled 870 // DIS Re Arm is disabled 871 #define SYSTIM_CH0CFG_REARM 0x00000008U 872 #define SYSTIM_CH0CFG_REARM_M 0x00000008U 873 #define SYSTIM_CH0CFG_REARM_S 3U 874 #define SYSTIM_CH0CFG_REARM_EN 0x00000008U 875 #define SYSTIM_CH0CFG_REARM_DIS 0x00000000U 876 877 // Field: [2:1] INP 878 // 879 // Decides the channel input signal's mode. Setting the Value as 2'b11 selects 880 // the Rise Function. 881 // ENUMs: 882 // BOTH Capture on both Edge 883 // FALL Capture on Falling Edge 884 // RISE Capture on rising edge 885 #define SYSTIM_CH0CFG_INP_W 2U 886 #define SYSTIM_CH0CFG_INP_M 0x00000006U 887 #define SYSTIM_CH0CFG_INP_S 1U 888 #define SYSTIM_CH0CFG_INP_BOTH 0x00000004U 889 #define SYSTIM_CH0CFG_INP_FALL 0x00000002U 890 #define SYSTIM_CH0CFG_INP_RISE 0x00000000U 891 892 // Field: [0] MODE 893 // 894 // Decides the channel mode. 895 // ENUMs: 896 // CAPT channel is in capture mode 897 // DIS channel is disabled 898 #define SYSTIM_CH0CFG_MODE 0x00000001U 899 #define SYSTIM_CH0CFG_MODE_M 0x00000001U 900 #define SYSTIM_CH0CFG_MODE_S 0U 901 #define SYSTIM_CH0CFG_MODE_CAPT 0x00000001U 902 #define SYSTIM_CH0CFG_MODE_DIS 0x00000000U 903 904 //***************************************************************************** 905 // 906 // Register: SYSTIM_O_CH1CFG 907 // 908 //***************************************************************************** 909 // Field: [3] REARM 910 // 911 // When Rearm is enabled the channel remains in continous capture mode. 912 // Otherwise it'll be in one shot capture mode. Rearm is only valid for capture 913 // mode. 914 // ENUMs: 915 // EN Re arm is enabled 916 // DIS Re Arm is disabled 917 #define SYSTIM_CH1CFG_REARM 0x00000008U 918 #define SYSTIM_CH1CFG_REARM_M 0x00000008U 919 #define SYSTIM_CH1CFG_REARM_S 3U 920 #define SYSTIM_CH1CFG_REARM_EN 0x00000008U 921 #define SYSTIM_CH1CFG_REARM_DIS 0x00000000U 922 923 // Field: [2:1] INP 924 // 925 // Decides the channel input signal's mode. Setting the Value as 2'b11 selects 926 // the Rise Function 927 // ENUMs: 928 // BOTH Capture on both Edge 929 // FALL Capture on Falling Edge 930 // RISE Capture on rising edge 931 #define SYSTIM_CH1CFG_INP_W 2U 932 #define SYSTIM_CH1CFG_INP_M 0x00000006U 933 #define SYSTIM_CH1CFG_INP_S 1U 934 #define SYSTIM_CH1CFG_INP_BOTH 0x00000004U 935 #define SYSTIM_CH1CFG_INP_FALL 0x00000002U 936 #define SYSTIM_CH1CFG_INP_RISE 0x00000000U 937 938 // Field: [0] MODE 939 // 940 // Decides the channel mode. 941 // ENUMs: 942 // CAPT channel is in capture mode 943 // DIS channel is disabled 944 #define SYSTIM_CH1CFG_MODE 0x00000001U 945 #define SYSTIM_CH1CFG_MODE_M 0x00000001U 946 #define SYSTIM_CH1CFG_MODE_S 0U 947 #define SYSTIM_CH1CFG_MODE_CAPT 0x00000001U 948 #define SYSTIM_CH1CFG_MODE_DIS 0x00000000U 949 950 //***************************************************************************** 951 // 952 // Register: SYSTIM_O_CH2CFG 953 // 954 //***************************************************************************** 955 // Field: [3] REARM 956 // 957 // When Rearm is enabled the channel remains in continous capture mode. 958 // Otherwise it'll be in one shot capture mode. Rearm is only valid for capture 959 // mode. 960 // ENUMs: 961 // EN Re arm is enabled 962 // DIS Re Arm is disabled 963 #define SYSTIM_CH2CFG_REARM 0x00000008U 964 #define SYSTIM_CH2CFG_REARM_M 0x00000008U 965 #define SYSTIM_CH2CFG_REARM_S 3U 966 #define SYSTIM_CH2CFG_REARM_EN 0x00000008U 967 #define SYSTIM_CH2CFG_REARM_DIS 0x00000000U 968 969 // Field: [2:1] INP 970 // 971 // Decides the channel input signal's mode. Setting the Value as 2'b11 selects 972 // the Rise Function 973 // ENUMs: 974 // BOTH Capture on both Edge 975 // FALL Capture on Falling Edge 976 // RISE Capture on rising edge 977 #define SYSTIM_CH2CFG_INP_W 2U 978 #define SYSTIM_CH2CFG_INP_M 0x00000006U 979 #define SYSTIM_CH2CFG_INP_S 1U 980 #define SYSTIM_CH2CFG_INP_BOTH 0x00000004U 981 #define SYSTIM_CH2CFG_INP_FALL 0x00000002U 982 #define SYSTIM_CH2CFG_INP_RISE 0x00000000U 983 984 // Field: [0] MODE 985 // 986 // Decides the channel mode. 987 // ENUMs: 988 // CAPT channel is in capture mode 989 // DIS channel is disabled 990 #define SYSTIM_CH2CFG_MODE 0x00000001U 991 #define SYSTIM_CH2CFG_MODE_M 0x00000001U 992 #define SYSTIM_CH2CFG_MODE_S 0U 993 #define SYSTIM_CH2CFG_MODE_CAPT 0x00000001U 994 #define SYSTIM_CH2CFG_MODE_DIS 0x00000000U 995 996 //***************************************************************************** 997 // 998 // Register: SYSTIM_O_CH3CFG 999 // 1000 //***************************************************************************** 1001 // Field: [3] REARM 1002 // 1003 // When Rearm is enabled the channel remains in continous capture mode. 1004 // Otherwise it'll be in one shot capture mode. Rearm is only valid for capture 1005 // mode. 1006 // ENUMs: 1007 // EN Re arm is enabled 1008 // DIS Re Arm is disabled 1009 #define SYSTIM_CH3CFG_REARM 0x00000008U 1010 #define SYSTIM_CH3CFG_REARM_M 0x00000008U 1011 #define SYSTIM_CH3CFG_REARM_S 3U 1012 #define SYSTIM_CH3CFG_REARM_EN 0x00000008U 1013 #define SYSTIM_CH3CFG_REARM_DIS 0x00000000U 1014 1015 // Field: [2:1] INP 1016 // 1017 // Decides the channel input signal's mode. Setting the Value as 2'b11 selects 1018 // the Rise Function 1019 // ENUMs: 1020 // BOTH Capture on both Edge 1021 // FALL Capture on Falling Edge 1022 // RISE Capture on rising edge 1023 #define SYSTIM_CH3CFG_INP_W 2U 1024 #define SYSTIM_CH3CFG_INP_M 0x00000006U 1025 #define SYSTIM_CH3CFG_INP_S 1U 1026 #define SYSTIM_CH3CFG_INP_BOTH 0x00000004U 1027 #define SYSTIM_CH3CFG_INP_FALL 0x00000002U 1028 #define SYSTIM_CH3CFG_INP_RISE 0x00000000U 1029 1030 // Field: [0] MODE 1031 // 1032 // Decides the channel mode. 1033 // ENUMs: 1034 // CAPT channel is in capture mode 1035 // DIS channel is disabled 1036 #define SYSTIM_CH3CFG_MODE 0x00000001U 1037 #define SYSTIM_CH3CFG_MODE_M 0x00000001U 1038 #define SYSTIM_CH3CFG_MODE_S 0U 1039 #define SYSTIM_CH3CFG_MODE_CAPT 0x00000001U 1040 #define SYSTIM_CH3CFG_MODE_DIS 0x00000000U 1041 1042 //***************************************************************************** 1043 // 1044 // Register: SYSTIM_O_CH4CFG 1045 // 1046 //***************************************************************************** 1047 // Field: [3] REARM 1048 // 1049 // When Rearm is enabled the channel remains in continous capture mode. 1050 // Otherwise it'll be in one shot capture mode. Rearm is only valid for capture 1051 // mode. 1052 // ENUMs: 1053 // EN Re arm is enabled 1054 // DIS Re Arm is disabled 1055 #define SYSTIM_CH4CFG_REARM 0x00000008U 1056 #define SYSTIM_CH4CFG_REARM_M 0x00000008U 1057 #define SYSTIM_CH4CFG_REARM_S 3U 1058 #define SYSTIM_CH4CFG_REARM_EN 0x00000008U 1059 #define SYSTIM_CH4CFG_REARM_DIS 0x00000000U 1060 1061 // Field: [2:1] INP 1062 // 1063 // Decides the channel input signal's mode. Setting the Value as 2'b11 selects 1064 // the Rise Function 1065 // ENUMs: 1066 // BOTH Capture on both Edge 1067 // FALL Capture on Falling Edge 1068 // RISE Capture on rising edge 1069 #define SYSTIM_CH4CFG_INP_W 2U 1070 #define SYSTIM_CH4CFG_INP_M 0x00000006U 1071 #define SYSTIM_CH4CFG_INP_S 1U 1072 #define SYSTIM_CH4CFG_INP_BOTH 0x00000004U 1073 #define SYSTIM_CH4CFG_INP_FALL 0x00000002U 1074 #define SYSTIM_CH4CFG_INP_RISE 0x00000000U 1075 1076 // Field: [0] MODE 1077 // 1078 // Decides the channel mode. 1079 // ENUMs: 1080 // CAPT channel is in capture mode 1081 // DIS channel is disabled 1082 #define SYSTIM_CH4CFG_MODE 0x00000001U 1083 #define SYSTIM_CH4CFG_MODE_M 0x00000001U 1084 #define SYSTIM_CH4CFG_MODE_S 0U 1085 #define SYSTIM_CH4CFG_MODE_CAPT 0x00000001U 1086 #define SYSTIM_CH4CFG_MODE_DIS 0x00000000U 1087 1088 //***************************************************************************** 1089 // 1090 // Register: SYSTIM_O_CH0CC 1091 // 1092 //***************************************************************************** 1093 // Field: [31:0] VAL 1094 // 1095 // Capture/compare value 1096 #define SYSTIM_CH0CC_VAL_W 32U 1097 #define SYSTIM_CH0CC_VAL_M 0xFFFFFFFFU 1098 #define SYSTIM_CH0CC_VAL_S 0U 1099 1100 //***************************************************************************** 1101 // 1102 // Register: SYSTIM_O_CH1CC 1103 // 1104 //***************************************************************************** 1105 // Field: [31:0] VAL 1106 // 1107 // Capture/compare value 1108 #define SYSTIM_CH1CC_VAL_W 32U 1109 #define SYSTIM_CH1CC_VAL_M 0xFFFFFFFFU 1110 #define SYSTIM_CH1CC_VAL_S 0U 1111 1112 //***************************************************************************** 1113 // 1114 // Register: SYSTIM_O_CH2CC 1115 // 1116 //***************************************************************************** 1117 // Field: [31:0] VAL 1118 // 1119 // Capture/compare value 1120 #define SYSTIM_CH2CC_VAL_W 32U 1121 #define SYSTIM_CH2CC_VAL_M 0xFFFFFFFFU 1122 #define SYSTIM_CH2CC_VAL_S 0U 1123 1124 //***************************************************************************** 1125 // 1126 // Register: SYSTIM_O_CH3CC 1127 // 1128 //***************************************************************************** 1129 // Field: [31:0] VAL 1130 // 1131 // Capture/compare value 1132 #define SYSTIM_CH3CC_VAL_W 32U 1133 #define SYSTIM_CH3CC_VAL_M 0xFFFFFFFFU 1134 #define SYSTIM_CH3CC_VAL_S 0U 1135 1136 //***************************************************************************** 1137 // 1138 // Register: SYSTIM_O_CH4CC 1139 // 1140 //***************************************************************************** 1141 // Field: [31:0] VAL 1142 // 1143 // Capture/compare value 1144 #define SYSTIM_CH4CC_VAL_W 32U 1145 #define SYSTIM_CH4CC_VAL_M 0xFFFFFFFFU 1146 #define SYSTIM_CH4CC_VAL_S 0U 1147 1148 //***************************************************************************** 1149 // 1150 // Register: SYSTIM_O_TIMEBIT 1151 // 1152 //***************************************************************************** 1153 // Field: [15:0] VAL 1154 // 1155 // The corresponding bit will have value '1' rest should be '0'. If more than 1156 // one bit is asserted, output is "or" of all the bits. 1157 // ENUMs: 1158 // BIT17 Bit17 is forwarded to the event fabric. 1159 // BIT16 Bit16 is forwarded to the event fabric. 1160 // BIT15 Bit15 is forwarded to the event fabric. 1161 // BIT14 Bit14 is forwarded to the event fabric. 1162 // BIT13 Bit13 is forwarded to the event fabric. 1163 // BIT12 Bit12 is forwarded to the event fabric. 1164 // BIT11 Bit11 is forwarded to the event fabric. 1165 // BIT10 Bit10 is forwarded to the event fabric. 1166 // BIT9 Bit9 is forwarded to the event fabric. 1167 // BIT8 Bit8 is forwarded to the event fabric. 1168 // BIT7 Bit7 is forwarded to the event fabric. 1169 // BIT6 Bit6 is forwarded to the event fabric. 1170 // BIT5 Bit5 is forwarded to the event fabric. 1171 // BIT4 Bit4 is forwarded to the event fabric. 1172 // BIT3 Bit3 is forwarded to the event fabric. 1173 // BIT2 Bit2 is forwarded to the event fabric. 1174 // NOBIT No bit is forwarded to the event fabric. 1175 #define SYSTIM_TIMEBIT_VAL_W 16U 1176 #define SYSTIM_TIMEBIT_VAL_M 0x0000FFFFU 1177 #define SYSTIM_TIMEBIT_VAL_S 0U 1178 #define SYSTIM_TIMEBIT_VAL_BIT17 0x00008000U 1179 #define SYSTIM_TIMEBIT_VAL_BIT16 0x00004000U 1180 #define SYSTIM_TIMEBIT_VAL_BIT15 0x00002000U 1181 #define SYSTIM_TIMEBIT_VAL_BIT14 0x00001000U 1182 #define SYSTIM_TIMEBIT_VAL_BIT13 0x00000800U 1183 #define SYSTIM_TIMEBIT_VAL_BIT12 0x00000400U 1184 #define SYSTIM_TIMEBIT_VAL_BIT11 0x00000200U 1185 #define SYSTIM_TIMEBIT_VAL_BIT10 0x00000100U 1186 #define SYSTIM_TIMEBIT_VAL_BIT9 0x00000080U 1187 #define SYSTIM_TIMEBIT_VAL_BIT8 0x00000040U 1188 #define SYSTIM_TIMEBIT_VAL_BIT7 0x00000020U 1189 #define SYSTIM_TIMEBIT_VAL_BIT6 0x00000010U 1190 #define SYSTIM_TIMEBIT_VAL_BIT5 0x00000008U 1191 #define SYSTIM_TIMEBIT_VAL_BIT4 0x00000004U 1192 #define SYSTIM_TIMEBIT_VAL_BIT3 0x00000002U 1193 #define SYSTIM_TIMEBIT_VAL_BIT2 0x00000001U 1194 #define SYSTIM_TIMEBIT_VAL_NOBIT 0x00000000U 1195 1196 //***************************************************************************** 1197 // 1198 // Register: SYSTIM_O_STATUS 1199 // 1200 //***************************************************************************** 1201 // Field: [4] SYNCUP 1202 // 1203 // This bit indicates sync status of Systimer with RTC. The bitfield has a 1204 // reset value of '1', which gets cleared to '0' after the Systimer 1205 // synchronizes with RTC on the first LFTICK edge. A write to this bit 1206 // resynchronizes the Systimer with RTC on the next LFTICK edge. A read value 1207 // of '1' indicates the synchronization is ongoing and a read of '0' indicates 1208 // the synchronization is done. 1209 #define SYSTIM_STATUS_SYNCUP 0x00000010U 1210 #define SYSTIM_STATUS_SYNCUP_M 0x00000010U 1211 #define SYSTIM_STATUS_SYNCUP_S 4U 1212 1213 // Field: [0] VAL 1214 // 1215 // This bit indicates if the system time is initialized and running. 1216 // ENUMs: 1217 // RUN system timer is running 1218 // STOP system timer is not running. 1219 #define SYSTIM_STATUS_VAL 0x00000001U 1220 #define SYSTIM_STATUS_VAL_M 0x00000001U 1221 #define SYSTIM_STATUS_VAL_S 0U 1222 #define SYSTIM_STATUS_VAL_RUN 0x00000001U 1223 #define SYSTIM_STATUS_VAL_STOP 0x00000000U 1224 1225 //***************************************************************************** 1226 // 1227 // Register: SYSTIM_O_ARMSET 1228 // 1229 //***************************************************************************** 1230 // Field: [4] CH4 1231 // 1232 // Arming channel 4 for either compare or capture operation. 1233 // ENUMs: 1234 // SET if channel 4 is in CAPTURE state then no effect on 1235 // the channel else it can set channel in COMPARE 1236 // mode using existing CH4CC.VAL value. 1237 // NOEFF No effect on the channel 1238 #define SYSTIM_ARMSET_CH4 0x00000010U 1239 #define SYSTIM_ARMSET_CH4_M 0x00000010U 1240 #define SYSTIM_ARMSET_CH4_S 4U 1241 #define SYSTIM_ARMSET_CH4_SET 0x00000010U 1242 #define SYSTIM_ARMSET_CH4_NOEFF 0x00000000U 1243 1244 // Field: [3] CH3 1245 // 1246 // Arming channel 3 for either compare or capture operation. 1247 // ENUMs: 1248 // SET if channel 3 is in CAPTURE state then no effect on 1249 // the channel else it can set channel in COMPARE 1250 // mode using existing CH3CC.VAL value 1251 // NOEFF No effect on the channel 1252 #define SYSTIM_ARMSET_CH3 0x00000008U 1253 #define SYSTIM_ARMSET_CH3_M 0x00000008U 1254 #define SYSTIM_ARMSET_CH3_S 3U 1255 #define SYSTIM_ARMSET_CH3_SET 0x00000008U 1256 #define SYSTIM_ARMSET_CH3_NOEFF 0x00000000U 1257 1258 // Field: [2] CH2 1259 // 1260 // Arming channel 2 for either compare or capture operation. 1261 // ENUMs: 1262 // SET if channel 2 is in CAPTURE state then no effect on 1263 // the channel else it can set channel in COMPARE 1264 // mode using existing CH2CC.VAL value 1265 // NOEFF No effect on the channel 1266 #define SYSTIM_ARMSET_CH2 0x00000004U 1267 #define SYSTIM_ARMSET_CH2_M 0x00000004U 1268 #define SYSTIM_ARMSET_CH2_S 2U 1269 #define SYSTIM_ARMSET_CH2_SET 0x00000004U 1270 #define SYSTIM_ARMSET_CH2_NOEFF 0x00000000U 1271 1272 // Field: [1] CH1 1273 // 1274 // Arming channel 1 for either compare or capture operation. 1275 // ENUMs: 1276 // SET if channel 1 is in CAPTURE state then no effect on 1277 // the channel else it can Set channel in COMPARE 1278 // mode using existing CH1CC.VAL value 1279 // NOEFF No effect on the channel 1280 #define SYSTIM_ARMSET_CH1 0x00000002U 1281 #define SYSTIM_ARMSET_CH1_M 0x00000002U 1282 #define SYSTIM_ARMSET_CH1_S 1U 1283 #define SYSTIM_ARMSET_CH1_SET 0x00000002U 1284 #define SYSTIM_ARMSET_CH1_NOEFF 0x00000000U 1285 1286 // Field: [0] CH0 1287 // 1288 // Arming channel 0 for either compare or capture operation. 1289 // ENUMs: 1290 // SET if channel 0 is in CAPTURE state then no effect on 1291 // the channel else it can set channel in COMPARE 1292 // mode using existing CH0CC.VAL value 1293 // NOEFF No effect on the channel 1294 #define SYSTIM_ARMSET_CH0 0x00000001U 1295 #define SYSTIM_ARMSET_CH0_M 0x00000001U 1296 #define SYSTIM_ARMSET_CH0_S 0U 1297 #define SYSTIM_ARMSET_CH0_SET 0x00000001U 1298 #define SYSTIM_ARMSET_CH0_NOEFF 0x00000000U 1299 1300 //***************************************************************************** 1301 // 1302 // Register: SYSTIM_O_ARMCLR 1303 // 1304 //***************************************************************************** 1305 // Field: [4] CH4 1306 // 1307 // Disarming channel 4 1308 // ENUMs: 1309 // CLR Set channel in UNARMED state without triggering 1310 // event unless a compare/capture event happens in 1311 // the same cycle 1312 // NOEFF No effect on the channel 1313 #define SYSTIM_ARMCLR_CH4 0x00000010U 1314 #define SYSTIM_ARMCLR_CH4_M 0x00000010U 1315 #define SYSTIM_ARMCLR_CH4_S 4U 1316 #define SYSTIM_ARMCLR_CH4_CLR 0x00000010U 1317 #define SYSTIM_ARMCLR_CH4_NOEFF 0x00000000U 1318 1319 // Field: [3] CH3 1320 // 1321 // Disarming channel 3 1322 // ENUMs: 1323 // CLR Set channel in UNARMED state without triggering 1324 // event unless a compare/capture event happens in 1325 // the same cycle 1326 // NOEFF No effect on the channel 1327 #define SYSTIM_ARMCLR_CH3 0x00000008U 1328 #define SYSTIM_ARMCLR_CH3_M 0x00000008U 1329 #define SYSTIM_ARMCLR_CH3_S 3U 1330 #define SYSTIM_ARMCLR_CH3_CLR 0x00000008U 1331 #define SYSTIM_ARMCLR_CH3_NOEFF 0x00000000U 1332 1333 // Field: [2] CH2 1334 // 1335 // Disarming channel 2 1336 // ENUMs: 1337 // CLR Set channel in UNARMED state without triggering 1338 // event unless a compare/capture event happens in 1339 // the same cycle 1340 // NOEFF No effect on the channel 1341 #define SYSTIM_ARMCLR_CH2 0x00000004U 1342 #define SYSTIM_ARMCLR_CH2_M 0x00000004U 1343 #define SYSTIM_ARMCLR_CH2_S 2U 1344 #define SYSTIM_ARMCLR_CH2_CLR 0x00000004U 1345 #define SYSTIM_ARMCLR_CH2_NOEFF 0x00000000U 1346 1347 // Field: [1] CH1 1348 // 1349 // Disarming channel 1 1350 // ENUMs: 1351 // CLR Set channel in UNARMED state without triggering 1352 // event unless a compare/capture event happens in 1353 // the same cycle 1354 // NOEFF No effect on the channel 1355 #define SYSTIM_ARMCLR_CH1 0x00000002U 1356 #define SYSTIM_ARMCLR_CH1_M 0x00000002U 1357 #define SYSTIM_ARMCLR_CH1_S 1U 1358 #define SYSTIM_ARMCLR_CH1_CLR 0x00000002U 1359 #define SYSTIM_ARMCLR_CH1_NOEFF 0x00000000U 1360 1361 // Field: [0] CH0 1362 // 1363 // Disarming channel 0 1364 // ENUMs: 1365 // CLR Set channel in UNARMED state without triggering 1366 // event unless a compare/capture event happens in 1367 // the same cycle 1368 // NOEFF No effect on the channel 1369 #define SYSTIM_ARMCLR_CH0 0x00000001U 1370 #define SYSTIM_ARMCLR_CH0_M 0x00000001U 1371 #define SYSTIM_ARMCLR_CH0_S 0U 1372 #define SYSTIM_ARMCLR_CH0_CLR 0x00000001U 1373 #define SYSTIM_ARMCLR_CH0_NOEFF 0x00000000U 1374 1375 //***************************************************************************** 1376 // 1377 // Register: SYSTIM_O_CH0CCSR 1378 // 1379 //***************************************************************************** 1380 // Field: [31:0] VAL 1381 // 1382 // Capture/compare value 1383 #define SYSTIM_CH0CCSR_VAL_W 32U 1384 #define SYSTIM_CH0CCSR_VAL_M 0xFFFFFFFFU 1385 #define SYSTIM_CH0CCSR_VAL_S 0U 1386 1387 //***************************************************************************** 1388 // 1389 // Register: SYSTIM_O_CH1CCSR 1390 // 1391 //***************************************************************************** 1392 // Field: [31:0] VAL 1393 // 1394 // Capture/compare value 1395 #define SYSTIM_CH1CCSR_VAL_W 32U 1396 #define SYSTIM_CH1CCSR_VAL_M 0xFFFFFFFFU 1397 #define SYSTIM_CH1CCSR_VAL_S 0U 1398 1399 //***************************************************************************** 1400 // 1401 // Register: SYSTIM_O_CH2CCSR 1402 // 1403 //***************************************************************************** 1404 // Field: [31:0] VAL 1405 // 1406 // Capture/compare value 1407 #define SYSTIM_CH2CCSR_VAL_W 32U 1408 #define SYSTIM_CH2CCSR_VAL_M 0xFFFFFFFFU 1409 #define SYSTIM_CH2CCSR_VAL_S 0U 1410 1411 //***************************************************************************** 1412 // 1413 // Register: SYSTIM_O_CH3CCSR 1414 // 1415 //***************************************************************************** 1416 // Field: [31:0] VAL 1417 // 1418 // Capture/compare value 1419 #define SYSTIM_CH3CCSR_VAL_W 32U 1420 #define SYSTIM_CH3CCSR_VAL_M 0xFFFFFFFFU 1421 #define SYSTIM_CH3CCSR_VAL_S 0U 1422 1423 //***************************************************************************** 1424 // 1425 // Register: SYSTIM_O_CH4CCSR 1426 // 1427 //***************************************************************************** 1428 // Field: [31:0] VAL 1429 // 1430 // Capture/compare value 1431 #define SYSTIM_CH4CCSR_VAL_W 32U 1432 #define SYSTIM_CH4CCSR_VAL_M 0xFFFFFFFFU 1433 #define SYSTIM_CH4CCSR_VAL_S 0U 1434 1435 1436 #endif // __SYSTIM__ 1437
