1 /****************************************************************************** 2 * Filename: hw_spi_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_SPI_H__ 34 #define __HW_SPI_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // SPI component 40 // 41 //***************************************************************************** 42 // Module Description 43 #define SPI_O_DESC 0x00000000U 44 45 // Interrupt mask 46 #define SPI_O_IMASK 0x00000044U 47 48 // Raw interrupt status 49 #define SPI_O_RIS 0x00000048U 50 51 // Masked interrupt status 52 #define SPI_O_MIS 0x0000004CU 53 54 // Interrupt set 55 #define SPI_O_ISET 0x00000050U 56 57 // Interrupt clear 58 #define SPI_O_ICLR 0x00000054U 59 60 // Interrupt mask set 61 #define SPI_O_IMSET 0x00000058U 62 63 // Interrupt mask clear 64 #define SPI_O_IMCLR 0x0000005CU 65 66 // Emulation 67 #define SPI_O_EMU 0x00000060U 68 69 // Control 0 70 #define SPI_O_CTL0 0x00000100U 71 72 // Control 1 73 #define SPI_O_CTL1 0x00000104U 74 75 // Clock configuration 0 76 #define SPI_O_CLKCFG0 0x00000108U 77 78 // Clock configuration 1 79 #define SPI_O_CLKCFG1 0x0000010CU 80 81 // Interrupt FIFO Level Select 82 #define SPI_O_IFLS 0x00000110U 83 84 // DMA control 85 #define SPI_O_DMACR 0x00000114U 86 87 // Receive CRC 88 #define SPI_O_RXCRC 0x00000118U 89 90 // Transmit CRC 91 #define SPI_O_TXCRC 0x0000011CU 92 93 // Header write for 32bits 94 #define SPI_O_TXFHDR32 0x00000120U 95 96 // Header write for 24bits 97 #define SPI_O_TXFHDR24 0x00000124U 98 99 // Header write for 16bits 100 #define SPI_O_TXFHDR16 0x00000128U 101 102 // Header write for 8bits 103 #define SPI_O_TXFHDR8 0x0000012CU 104 105 // Atomic header control 106 #define SPI_O_TXFHDRC 0x00000130U 107 108 // Receive data 109 #define SPI_O_RXDATA 0x00000140U 110 111 // Transmit data 112 #define SPI_O_TXDATA 0x00000150U 113 114 // Status 115 #define SPI_O_STA 0x00000160U 116 117 //***************************************************************************** 118 // 119 // Register: SPI_O_DESC 120 // 121 //***************************************************************************** 122 // Field: [31:16] MODID 123 // 124 // Module identifier used to uniquely identify this IP. 125 #define SPI_DESC_MODID_W 16U 126 #define SPI_DESC_MODID_M 0xFFFF0000U 127 #define SPI_DESC_MODID_S 16U 128 129 // Field: [15:12] STDIPOFF 130 // 131 // Standard IP MMR block offset. Standard IP MMRs are the set of from 132 // aggregated IRQ registers till DTB. 133 // 134 // 0: Standard IP MMRs do not exist 135 // 136 // 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP 137 // address) 138 #define SPI_DESC_STDIPOFF_W 4U 139 #define SPI_DESC_STDIPOFF_M 0x0000F000U 140 #define SPI_DESC_STDIPOFF_S 12U 141 142 // Field: [11:8] INSTIDX 143 // 144 // IP Instance ID number. If multiple instances of IP exist in the device, this 145 // field can identify the instance number (0-15). 146 #define SPI_DESC_INSTIDX_W 4U 147 #define SPI_DESC_INSTIDX_M 0x00000F00U 148 #define SPI_DESC_INSTIDX_S 8U 149 150 // Field: [7:4] MAJREV 151 // 152 // Major revision of IP (0-15). 153 #define SPI_DESC_MAJREV_W 4U 154 #define SPI_DESC_MAJREV_M 0x000000F0U 155 #define SPI_DESC_MAJREV_S 4U 156 157 // Field: [3:0] MINREV 158 // 159 // Minor revision of IP (0-15). 160 #define SPI_DESC_MINREV_W 4U 161 #define SPI_DESC_MINREV_M 0x0000000FU 162 #define SPI_DESC_MINREV_S 0U 163 164 //***************************************************************************** 165 // 166 // Register: SPI_O_IMASK 167 // 168 //***************************************************************************** 169 // Field: [8] DMATX 170 // 171 // DMA Done TX event mask. 172 // ENUMs: 173 // SET Set Interrupt Mask 174 // CLR Clear Interrupt Mask 175 #define SPI_IMASK_DMATX 0x00000100U 176 #define SPI_IMASK_DMATX_M 0x00000100U 177 #define SPI_IMASK_DMATX_S 8U 178 #define SPI_IMASK_DMATX_SET 0x00000100U 179 #define SPI_IMASK_DMATX_CLR 0x00000000U 180 181 // Field: [7] DMARX 182 // 183 // DMA Done RX event mask. 184 // ENUMs: 185 // SET Set Interrrupt Mask 186 // CLR Clear Interrupt Mask 187 #define SPI_IMASK_DMARX 0x00000080U 188 #define SPI_IMASK_DMARX_M 0x00000080U 189 #define SPI_IMASK_DMARX_S 7U 190 #define SPI_IMASK_DMARX_SET 0x00000080U 191 #define SPI_IMASK_DMARX_CLR 0x00000000U 192 193 // Field: [6] IDLE 194 // 195 // SPI Idle event mask. 196 // ENUMs: 197 // SET Set Interrrupt Mask 198 // CLR Clear Interrupt Mask 199 #define SPI_IMASK_IDLE 0x00000040U 200 #define SPI_IMASK_IDLE_M 0x00000040U 201 #define SPI_IMASK_IDLE_S 6U 202 #define SPI_IMASK_IDLE_SET 0x00000040U 203 #define SPI_IMASK_IDLE_CLR 0x00000000U 204 205 // Field: [5] TXEMPTY 206 // 207 // Transmit FIFO Empty event mask. 208 // ENUMs: 209 // SET Set Interrrupt Mask 210 // CLR Clear Interrupt Mask 211 #define SPI_IMASK_TXEMPTY 0x00000020U 212 #define SPI_IMASK_TXEMPTY_M 0x00000020U 213 #define SPI_IMASK_TXEMPTY_S 5U 214 #define SPI_IMASK_TXEMPTY_SET 0x00000020U 215 #define SPI_IMASK_TXEMPTY_CLR 0x00000000U 216 217 // Field: [4] TX 218 // 219 // Transmit FIFO event mask. 220 // ENUMs: 221 // SET Set Interrrupt Mask 222 // CLR Clear Interrupt Mask 223 #define SPI_IMASK_TX 0x00000010U 224 #define SPI_IMASK_TX_M 0x00000010U 225 #define SPI_IMASK_TX_S 4U 226 #define SPI_IMASK_TX_SET 0x00000010U 227 #define SPI_IMASK_TX_CLR 0x00000000U 228 229 // Field: [3] RX 230 // 231 // Receive FIFO event. 232 // ENUMs: 233 // SET Set Interrrupt Mask 234 // CLR Clear Interrupt Mask 235 #define SPI_IMASK_RX 0x00000008U 236 #define SPI_IMASK_RX_M 0x00000008U 237 #define SPI_IMASK_RX_S 3U 238 #define SPI_IMASK_RX_SET 0x00000008U 239 #define SPI_IMASK_RX_CLR 0x00000000U 240 241 // Field: [2] RTOUT 242 // 243 // SPI Receive Time-Out event mask. 244 // ENUMs: 245 // SET Set Interrrupt Mask 246 // CLR Clear Interrupt Mask 247 #define SPI_IMASK_RTOUT 0x00000004U 248 #define SPI_IMASK_RTOUT_M 0x00000004U 249 #define SPI_IMASK_RTOUT_S 2U 250 #define SPI_IMASK_RTOUT_SET 0x00000004U 251 #define SPI_IMASK_RTOUT_CLR 0x00000000U 252 253 // Field: [1] PER 254 // 255 // Parity error event mask. 256 // ENUMs: 257 // SET Set Interrrupt Mask 258 // CLR Clear Interrupt Mask 259 #define SPI_IMASK_PER 0x00000002U 260 #define SPI_IMASK_PER_M 0x00000002U 261 #define SPI_IMASK_PER_S 1U 262 #define SPI_IMASK_PER_SET 0x00000002U 263 #define SPI_IMASK_PER_CLR 0x00000000U 264 265 // Field: [0] RXOVF 266 // 267 // RXFIFO overflow event mask. 268 // ENUMs: 269 // SET Set Interrrupt Mask 270 // CLR Clear Interrupt Mask 271 #define SPI_IMASK_RXOVF 0x00000001U 272 #define SPI_IMASK_RXOVF_M 0x00000001U 273 #define SPI_IMASK_RXOVF_S 0U 274 #define SPI_IMASK_RXOVF_SET 0x00000001U 275 #define SPI_IMASK_RXOVF_CLR 0x00000000U 276 277 //***************************************************************************** 278 // 279 // Register: SPI_O_RIS 280 // 281 //***************************************************************************** 282 // Field: [8] DMATX 283 // 284 // DMA Done event for TX. This interrupt is set if the TX DMA channel sends the 285 // DONE signal. This allows the handling of the TX DMA event inside SPI. 286 // ENUMs: 287 // SET Interrupt occurred 288 // CLR Interrupt did not occur 289 #define SPI_RIS_DMATX 0x00000100U 290 #define SPI_RIS_DMATX_M 0x00000100U 291 #define SPI_RIS_DMATX_S 8U 292 #define SPI_RIS_DMATX_SET 0x00000100U 293 #define SPI_RIS_DMATX_CLR 0x00000000U 294 295 // Field: [7] DMARX 296 // 297 // DMA Done event for RX. This interrupt is set if the RX DMA channel sends the 298 // DONE signal. This allows handling of the DMA RX event inside SPI. 299 // ENUMs: 300 // SET Interrupt occurred 301 // CLR Interrupt did not occur 302 #define SPI_RIS_DMARX 0x00000080U 303 #define SPI_RIS_DMARX_M 0x00000080U 304 #define SPI_RIS_DMARX_S 7U 305 #define SPI_RIS_DMARX_SET 0x00000080U 306 #define SPI_RIS_DMARX_CLR 0x00000000U 307 308 // Field: [6] IDLE 309 // 310 // SPI has completed transfers and moved to IDLE mode. This bit is set when 311 // STA.BUSY goes low. 312 // ENUMs: 313 // SET Interrupt occurred 314 // CLR Interrupt did not occur 315 #define SPI_RIS_IDLE 0x00000040U 316 #define SPI_RIS_IDLE_M 0x00000040U 317 #define SPI_RIS_IDLE_S 6U 318 #define SPI_RIS_IDLE_SET 0x00000040U 319 #define SPI_RIS_IDLE_CLR 0x00000000U 320 321 // Field: [5] TXEMPTY 322 // 323 // Transmit FIFO Empty interrupt mask. This interrupt is set when all data in 324 // the Transmit FIFO has been moved to the shift register. 325 // ENUMs: 326 // SET Interrupt occurred 327 // CLR Interrupt did not occur 328 #define SPI_RIS_TXEMPTY 0x00000020U 329 #define SPI_RIS_TXEMPTY_M 0x00000020U 330 #define SPI_RIS_TXEMPTY_S 5U 331 #define SPI_RIS_TXEMPTY_SET 0x00000020U 332 #define SPI_RIS_TXEMPTY_CLR 0x00000000U 333 334 // Field: [4] TX 335 // 336 // Transmit FIFO event. This interrupt is set if the selected Transmit FIFO 337 // level has been reached. 338 // ENUMs: 339 // SET Interrupt occurred 340 // CLR Interrupt did not occur 341 #define SPI_RIS_TX 0x00000010U 342 #define SPI_RIS_TX_M 0x00000010U 343 #define SPI_RIS_TX_S 4U 344 #define SPI_RIS_TX_SET 0x00000010U 345 #define SPI_RIS_TX_CLR 0x00000000U 346 347 // Field: [3] RX 348 // 349 // Receive FIFO event. This interrupt is set if the selected Receive FIFO level 350 // has been reached 351 // ENUMs: 352 // SET Interrupt occurred 353 // CLR Interrupt did not occur 354 #define SPI_RIS_RX 0x00000008U 355 #define SPI_RIS_RX_M 0x00000008U 356 #define SPI_RIS_RX_S 3U 357 #define SPI_RIS_RX_SET 0x00000008U 358 #define SPI_RIS_RX_CLR 0x00000000U 359 360 // Field: [2] RTOUT 361 // 362 // SPI Receive Time-Out event. This interrupt is set if no activity is detected 363 // on the input clock line within the time period dictated by CTL1.RTOUT value. 364 // This is applicable only in peripheral mode. 365 // ENUMs: 366 // SET Interrupt occurred 367 // CLR Interrupt did not occur 368 #define SPI_RIS_RTOUT 0x00000004U 369 #define SPI_RIS_RTOUT_M 0x00000004U 370 #define SPI_RIS_RTOUT_S 2U 371 #define SPI_RIS_RTOUT_SET 0x00000004U 372 #define SPI_RIS_RTOUT_CLR 0x00000000U 373 374 // Field: [1] PER 375 // 376 // Parity error event. This bit is set if a Parity error has been detected 377 // ENUMs: 378 // SET Interrupt occurred 379 // CLR Interrupt did not occur 380 #define SPI_RIS_PER 0x00000002U 381 #define SPI_RIS_PER_M 0x00000002U 382 #define SPI_RIS_PER_S 1U 383 #define SPI_RIS_PER_SET 0x00000002U 384 #define SPI_RIS_PER_CLR 0x00000000U 385 386 // Field: [0] RXOVF 387 // 388 // RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been 389 // detected. 390 // ENUMs: 391 // SET Interrupt occurred 392 // CLR Interrupt did not occur 393 #define SPI_RIS_RXOVF 0x00000001U 394 #define SPI_RIS_RXOVF_M 0x00000001U 395 #define SPI_RIS_RXOVF_S 0U 396 #define SPI_RIS_RXOVF_SET 0x00000001U 397 #define SPI_RIS_RXOVF_CLR 0x00000000U 398 399 //***************************************************************************** 400 // 401 // Register: SPI_O_MIS 402 // 403 //***************************************************************************** 404 // Field: [8] DMATX 405 // 406 // Masked DMA Done event for TX. 407 // ENUMs: 408 // SET Interrupt occurred 409 // CLR Interrupt did not occur 410 #define SPI_MIS_DMATX 0x00000100U 411 #define SPI_MIS_DMATX_M 0x00000100U 412 #define SPI_MIS_DMATX_S 8U 413 #define SPI_MIS_DMATX_SET 0x00000100U 414 #define SPI_MIS_DMATX_CLR 0x00000000U 415 416 // Field: [7] DMARX 417 // 418 // Masked DMA Done event for RX. 419 // ENUMs: 420 // SET Interrupt occurred 421 // CLR Interrupt did not occur 422 #define SPI_MIS_DMARX 0x00000080U 423 #define SPI_MIS_DMARX_M 0x00000080U 424 #define SPI_MIS_DMARX_S 7U 425 #define SPI_MIS_DMARX_SET 0x00000080U 426 #define SPI_MIS_DMARX_CLR 0x00000000U 427 428 // Field: [6] IDLE 429 // 430 // Masked SPI IDLE event. 431 // ENUMs: 432 // SET Interrupt occurred 433 // CLR Interrupt did not occur 434 #define SPI_MIS_IDLE 0x00000040U 435 #define SPI_MIS_IDLE_M 0x00000040U 436 #define SPI_MIS_IDLE_S 6U 437 #define SPI_MIS_IDLE_SET 0x00000040U 438 #define SPI_MIS_IDLE_CLR 0x00000000U 439 440 // Field: [5] TXEMPTY 441 // 442 // Masked Transmit FIFO Empty event. 443 // ENUMs: 444 // SET Interrupt occurred 445 // CLR Interrupt did not occur 446 #define SPI_MIS_TXEMPTY 0x00000020U 447 #define SPI_MIS_TXEMPTY_M 0x00000020U 448 #define SPI_MIS_TXEMPTY_S 5U 449 #define SPI_MIS_TXEMPTY_SET 0x00000020U 450 #define SPI_MIS_TXEMPTY_CLR 0x00000000U 451 452 // Field: [4] TX 453 // 454 // Masked Transmit FIFO event. 455 // ENUMs: 456 // SET Interrupt occurred 457 // CLR Interrupt did not occur 458 #define SPI_MIS_TX 0x00000010U 459 #define SPI_MIS_TX_M 0x00000010U 460 #define SPI_MIS_TX_S 4U 461 #define SPI_MIS_TX_SET 0x00000010U 462 #define SPI_MIS_TX_CLR 0x00000000U 463 464 // Field: [3] RX 465 // 466 // Masked Receive FIFO event. 467 // ENUMs: 468 // SET Interrupt occurred 469 // CLR Interrupt did not occur 470 #define SPI_MIS_RX 0x00000008U 471 #define SPI_MIS_RX_M 0x00000008U 472 #define SPI_MIS_RX_S 3U 473 #define SPI_MIS_RX_SET 0x00000008U 474 #define SPI_MIS_RX_CLR 0x00000000U 475 476 // Field: [2] RTOUT 477 // 478 // Masked SPI Receive Time-Out event. 479 // ENUMs: 480 // SET Interrupt occurred 481 // CLR Interrupt did not occur 482 #define SPI_MIS_RTOUT 0x00000004U 483 #define SPI_MIS_RTOUT_M 0x00000004U 484 #define SPI_MIS_RTOUT_S 2U 485 #define SPI_MIS_RTOUT_SET 0x00000004U 486 #define SPI_MIS_RTOUT_CLR 0x00000000U 487 488 // Field: [1] PER 489 // 490 // Masked Parity error event. 491 // ENUMs: 492 // SET Interrupt occurred 493 // CLR Interrupt did not occur 494 #define SPI_MIS_PER 0x00000002U 495 #define SPI_MIS_PER_M 0x00000002U 496 #define SPI_MIS_PER_S 1U 497 #define SPI_MIS_PER_SET 0x00000002U 498 #define SPI_MIS_PER_CLR 0x00000000U 499 500 // Field: [0] RXOVF 501 // 502 // Masked RXFIFO overflow event. 503 // ENUMs: 504 // SET Interrupt occurred 505 // CLR Interrupt did not occur 506 #define SPI_MIS_RXOVF 0x00000001U 507 #define SPI_MIS_RXOVF_M 0x00000001U 508 #define SPI_MIS_RXOVF_S 0U 509 #define SPI_MIS_RXOVF_SET 0x00000001U 510 #define SPI_MIS_RXOVF_CLR 0x00000000U 511 512 //***************************************************************************** 513 // 514 // Register: SPI_O_ISET 515 // 516 //***************************************************************************** 517 // Field: [8] DMATX 518 // 519 // Set DMA Done event for TX. 520 // ENUMs: 521 // SET Set Interrupt 522 // NOEFF Writing 0 has no effect 523 #define SPI_ISET_DMATX 0x00000100U 524 #define SPI_ISET_DMATX_M 0x00000100U 525 #define SPI_ISET_DMATX_S 8U 526 #define SPI_ISET_DMATX_SET 0x00000100U 527 #define SPI_ISET_DMATX_NOEFF 0x00000000U 528 529 // Field: [7] DMARX 530 // 531 // Set DMA Done event for RX. 532 // ENUMs: 533 // SET Set Interrupt 534 // NOEFF Writing 0 has no effect 535 #define SPI_ISET_DMARX 0x00000080U 536 #define SPI_ISET_DMARX_M 0x00000080U 537 #define SPI_ISET_DMARX_S 7U 538 #define SPI_ISET_DMARX_SET 0x00000080U 539 #define SPI_ISET_DMARX_NOEFF 0x00000000U 540 541 // Field: [6] IDLE 542 // 543 // Set SPI IDLE event. 544 // ENUMs: 545 // SET Set Interrupt 546 // NOEFF Writing 0 has no effect 547 #define SPI_ISET_IDLE 0x00000040U 548 #define SPI_ISET_IDLE_M 0x00000040U 549 #define SPI_ISET_IDLE_S 6U 550 #define SPI_ISET_IDLE_SET 0x00000040U 551 #define SPI_ISET_IDLE_NOEFF 0x00000000U 552 553 // Field: [5] TXEMPTY 554 // 555 // Set Transmit FIFO Empty event. 556 // ENUMs: 557 // SET Set Interrupt 558 // NOEFF Writing 0 has no effect 559 #define SPI_ISET_TXEMPTY 0x00000020U 560 #define SPI_ISET_TXEMPTY_M 0x00000020U 561 #define SPI_ISET_TXEMPTY_S 5U 562 #define SPI_ISET_TXEMPTY_SET 0x00000020U 563 #define SPI_ISET_TXEMPTY_NOEFF 0x00000000U 564 565 // Field: [4] TX 566 // 567 // Set Transmit FIFO event. 568 // ENUMs: 569 // SET Set Interrupt 570 // NOEFF Writing 0 has no effect 571 #define SPI_ISET_TX 0x00000010U 572 #define SPI_ISET_TX_M 0x00000010U 573 #define SPI_ISET_TX_S 4U 574 #define SPI_ISET_TX_SET 0x00000010U 575 #define SPI_ISET_TX_NOEFF 0x00000000U 576 577 // Field: [3] RX 578 // 579 // Set Receive FIFO event. 580 // ENUMs: 581 // SET Set Interrupt 582 // NOEFF Writing 0 has no effect 583 #define SPI_ISET_RX 0x00000008U 584 #define SPI_ISET_RX_M 0x00000008U 585 #define SPI_ISET_RX_S 3U 586 #define SPI_ISET_RX_SET 0x00000008U 587 #define SPI_ISET_RX_NOEFF 0x00000000U 588 589 // Field: [2] RTOUT 590 // 591 // Set SPI Receive Time-Out Event. 592 // ENUMs: 593 // SET Set Interrupt Mask 594 // NOEFF Writing 0 has no effect 595 #define SPI_ISET_RTOUT 0x00000004U 596 #define SPI_ISET_RTOUT_M 0x00000004U 597 #define SPI_ISET_RTOUT_S 2U 598 #define SPI_ISET_RTOUT_SET 0x00000004U 599 #define SPI_ISET_RTOUT_NOEFF 0x00000000U 600 601 // Field: [1] PER 602 // 603 // Set Parity error event. 604 // ENUMs: 605 // SET Set Interrupt 606 // NOEFF Writing 0 has no effect 607 #define SPI_ISET_PER 0x00000002U 608 #define SPI_ISET_PER_M 0x00000002U 609 #define SPI_ISET_PER_S 1U 610 #define SPI_ISET_PER_SET 0x00000002U 611 #define SPI_ISET_PER_NOEFF 0x00000000U 612 613 // Field: [0] RXOVF 614 // 615 // Set RXFIFO overflow event. 616 // ENUMs: 617 // SET Set Interrupt 618 // NOEFF Writing 0 has no effect 619 #define SPI_ISET_RXOVF 0x00000001U 620 #define SPI_ISET_RXOVF_M 0x00000001U 621 #define SPI_ISET_RXOVF_S 0U 622 #define SPI_ISET_RXOVF_SET 0x00000001U 623 #define SPI_ISET_RXOVF_NOEFF 0x00000000U 624 625 //***************************************************************************** 626 // 627 // Register: SPI_O_ICLR 628 // 629 //***************************************************************************** 630 // Field: [8] DMATX 631 // 632 // Clear DMA Done event for TX. 633 // ENUMs: 634 // CLR Clear Interrupt 635 // NOEFF Writing 0 has no effect 636 #define SPI_ICLR_DMATX 0x00000100U 637 #define SPI_ICLR_DMATX_M 0x00000100U 638 #define SPI_ICLR_DMATX_S 8U 639 #define SPI_ICLR_DMATX_CLR 0x00000100U 640 #define SPI_ICLR_DMATX_NOEFF 0x00000000U 641 642 // Field: [7] DMARX 643 // 644 // Clear DMA Done event for RX. 645 // ENUMs: 646 // CLR Clear Interrupt 647 // NOEFF Writing 0 has no effect 648 #define SPI_ICLR_DMARX 0x00000080U 649 #define SPI_ICLR_DMARX_M 0x00000080U 650 #define SPI_ICLR_DMARX_S 7U 651 #define SPI_ICLR_DMARX_CLR 0x00000080U 652 #define SPI_ICLR_DMARX_NOEFF 0x00000000U 653 654 // Field: [6] IDLE 655 // 656 // Clear SPI IDLE event. 657 // ENUMs: 658 // CLR Clear Interrupt 659 // NOEFF Writing 0 has no effect 660 #define SPI_ICLR_IDLE 0x00000040U 661 #define SPI_ICLR_IDLE_M 0x00000040U 662 #define SPI_ICLR_IDLE_S 6U 663 #define SPI_ICLR_IDLE_CLR 0x00000040U 664 #define SPI_ICLR_IDLE_NOEFF 0x00000000U 665 666 // Field: [5] TXEMPTY 667 // 668 // Clear Transmit FIFO Empty event. 669 // ENUMs: 670 // CLR Clear Interrupt 671 // NOEFF Writing 0 has no effect 672 #define SPI_ICLR_TXEMPTY 0x00000020U 673 #define SPI_ICLR_TXEMPTY_M 0x00000020U 674 #define SPI_ICLR_TXEMPTY_S 5U 675 #define SPI_ICLR_TXEMPTY_CLR 0x00000020U 676 #define SPI_ICLR_TXEMPTY_NOEFF 0x00000000U 677 678 // Field: [4] TX 679 // 680 // Clear Transmit FIFO event. 681 // ENUMs: 682 // CLR Clear Interrupt 683 // NOEFF Writing 0 has no effect 684 #define SPI_ICLR_TX 0x00000010U 685 #define SPI_ICLR_TX_M 0x00000010U 686 #define SPI_ICLR_TX_S 4U 687 #define SPI_ICLR_TX_CLR 0x00000010U 688 #define SPI_ICLR_TX_NOEFF 0x00000000U 689 690 // Field: [3] RX 691 // 692 // Clear Receive FIFO event. 693 // ENUMs: 694 // CLR Clear Interrupt 695 // NOEFF Writing 0 has no effect 696 #define SPI_ICLR_RX 0x00000008U 697 #define SPI_ICLR_RX_M 0x00000008U 698 #define SPI_ICLR_RX_S 3U 699 #define SPI_ICLR_RX_CLR 0x00000008U 700 #define SPI_ICLR_RX_NOEFF 0x00000000U 701 702 // Field: [2] RTOUT 703 // 704 // Clear SPI Receive Time-Out Event. 705 // ENUMs: 706 // CLR Set Interrupt Mask 707 // NOEFF Writing 0 has no effect 708 #define SPI_ICLR_RTOUT 0x00000004U 709 #define SPI_ICLR_RTOUT_M 0x00000004U 710 #define SPI_ICLR_RTOUT_S 2U 711 #define SPI_ICLR_RTOUT_CLR 0x00000004U 712 #define SPI_ICLR_RTOUT_NOEFF 0x00000000U 713 714 // Field: [1] PER 715 // 716 // Clear Parity error event. 717 // ENUMs: 718 // CLR Clear Interrupt 719 // NOEFF Writing 0 has no effect 720 #define SPI_ICLR_PER 0x00000002U 721 #define SPI_ICLR_PER_M 0x00000002U 722 #define SPI_ICLR_PER_S 1U 723 #define SPI_ICLR_PER_CLR 0x00000002U 724 #define SPI_ICLR_PER_NOEFF 0x00000000U 725 726 // Field: [0] RXOVF 727 // 728 // Clear RXFIFO overflow event. 729 // ENUMs: 730 // CLR Clear Interrupt 731 // NOEFF Writing 0 has no effect 732 #define SPI_ICLR_RXOVF 0x00000001U 733 #define SPI_ICLR_RXOVF_M 0x00000001U 734 #define SPI_ICLR_RXOVF_S 0U 735 #define SPI_ICLR_RXOVF_CLR 0x00000001U 736 #define SPI_ICLR_RXOVF_NOEFF 0x00000000U 737 738 //***************************************************************************** 739 // 740 // Register: SPI_O_IMSET 741 // 742 //***************************************************************************** 743 // Field: [8] DMATX 744 // 745 // Set DMA Done for TX event mask 746 // ENUMs: 747 // SET Set interrupt mask 748 // NOEFF Writing 0 has no effect 749 #define SPI_IMSET_DMATX 0x00000100U 750 #define SPI_IMSET_DMATX_M 0x00000100U 751 #define SPI_IMSET_DMATX_S 8U 752 #define SPI_IMSET_DMATX_SET 0x00000100U 753 #define SPI_IMSET_DMATX_NOEFF 0x00000000U 754 755 // Field: [7] DMARX 756 // 757 // Set DMA Done for RX event mask 758 // ENUMs: 759 // SET Set interrupt mask 760 // NOEFF Writing 0 has no effect 761 #define SPI_IMSET_DMARX 0x00000080U 762 #define SPI_IMSET_DMARX_M 0x00000080U 763 #define SPI_IMSET_DMARX_S 7U 764 #define SPI_IMSET_DMARX_SET 0x00000080U 765 #define SPI_IMSET_DMARX_NOEFF 0x00000000U 766 767 // Field: [6] IDLE 768 // 769 // Set SPI IDLE event mask 770 // ENUMs: 771 // SET Set interrupt mask 772 // NOEFF Writing 0 has no effect 773 #define SPI_IMSET_IDLE 0x00000040U 774 #define SPI_IMSET_IDLE_M 0x00000040U 775 #define SPI_IMSET_IDLE_S 6U 776 #define SPI_IMSET_IDLE_SET 0x00000040U 777 #define SPI_IMSET_IDLE_NOEFF 0x00000000U 778 779 // Field: [5] TXEMPTY 780 // 781 // Set Transmit FIFO Empty event mask 782 // ENUMs: 783 // SET Set interrupt mask 784 // NOEFF Writing 0 has no effect 785 #define SPI_IMSET_TXEMPTY 0x00000020U 786 #define SPI_IMSET_TXEMPTY_M 0x00000020U 787 #define SPI_IMSET_TXEMPTY_S 5U 788 #define SPI_IMSET_TXEMPTY_SET 0x00000020U 789 #define SPI_IMSET_TXEMPTY_NOEFF 0x00000000U 790 791 // Field: [4] TX 792 // 793 // Set Transmit FIFO event mask 794 // ENUMs: 795 // SET Set interrupt mask 796 // NOEFF Writing 0 has no effect 797 #define SPI_IMSET_TX 0x00000010U 798 #define SPI_IMSET_TX_M 0x00000010U 799 #define SPI_IMSET_TX_S 4U 800 #define SPI_IMSET_TX_SET 0x00000010U 801 #define SPI_IMSET_TX_NOEFF 0x00000000U 802 803 // Field: [3] RX 804 // 805 // Set Receive FIFO event mask 806 // ENUMs: 807 // SET Set interrupt mask 808 // NOEFF Writing 0 has no effect 809 #define SPI_IMSET_RX 0x00000008U 810 #define SPI_IMSET_RX_M 0x00000008U 811 #define SPI_IMSET_RX_S 3U 812 #define SPI_IMSET_RX_SET 0x00000008U 813 #define SPI_IMSET_RX_NOEFF 0x00000000U 814 815 // Field: [2] RTOUT 816 // 817 // Set SPI Receive Time-Out event mask 818 // ENUMs: 819 // SET Set interrupt mask 820 // NOEFF Writing 0 has no effect 821 #define SPI_IMSET_RTOUT 0x00000004U 822 #define SPI_IMSET_RTOUT_M 0x00000004U 823 #define SPI_IMSET_RTOUT_S 2U 824 #define SPI_IMSET_RTOUT_SET 0x00000004U 825 #define SPI_IMSET_RTOUT_NOEFF 0x00000000U 826 827 // Field: [1] PER 828 // 829 // Set Parity error event mask 830 // ENUMs: 831 // SET Set interrupt mask 832 // NOEFF Writing 0 has no effect 833 #define SPI_IMSET_PER 0x00000002U 834 #define SPI_IMSET_PER_M 0x00000002U 835 #define SPI_IMSET_PER_S 1U 836 #define SPI_IMSET_PER_SET 0x00000002U 837 #define SPI_IMSET_PER_NOEFF 0x00000000U 838 839 // Field: [0] RXOVF 840 // 841 // Set RXFIFO overflow event mask 842 // ENUMs: 843 // SET Set interrupt mask 844 // NOEFF Writing 0 has no effect 845 #define SPI_IMSET_RXOVF 0x00000001U 846 #define SPI_IMSET_RXOVF_M 0x00000001U 847 #define SPI_IMSET_RXOVF_S 0U 848 #define SPI_IMSET_RXOVF_SET 0x00000001U 849 #define SPI_IMSET_RXOVF_NOEFF 0x00000000U 850 851 //***************************************************************************** 852 // 853 // Register: SPI_O_IMCLR 854 // 855 //***************************************************************************** 856 // Field: [8] DMATX 857 // 858 // Clear DMA Done for TX event mask 859 // ENUMs: 860 // CLR Clear interrupt mask 861 // NOEFF Writing 0 has no effect 862 #define SPI_IMCLR_DMATX 0x00000100U 863 #define SPI_IMCLR_DMATX_M 0x00000100U 864 #define SPI_IMCLR_DMATX_S 8U 865 #define SPI_IMCLR_DMATX_CLR 0x00000100U 866 #define SPI_IMCLR_DMATX_NOEFF 0x00000000U 867 868 // Field: [7] DMARX 869 // 870 // Clear DMA Done for RX event mask 871 // ENUMs: 872 // CLR Clear interrupt mask 873 // NOEFF Writing 0 has no effect 874 #define SPI_IMCLR_DMARX 0x00000080U 875 #define SPI_IMCLR_DMARX_M 0x00000080U 876 #define SPI_IMCLR_DMARX_S 7U 877 #define SPI_IMCLR_DMARX_CLR 0x00000080U 878 #define SPI_IMCLR_DMARX_NOEFF 0x00000000U 879 880 // Field: [6] IDLE 881 // 882 // Clear SPI IDLE event mask 883 // ENUMs: 884 // CLR Clear interrupt mask 885 // NOEFF Writing 0 has no effect 886 #define SPI_IMCLR_IDLE 0x00000040U 887 #define SPI_IMCLR_IDLE_M 0x00000040U 888 #define SPI_IMCLR_IDLE_S 6U 889 #define SPI_IMCLR_IDLE_CLR 0x00000040U 890 #define SPI_IMCLR_IDLE_NOEFF 0x00000000U 891 892 // Field: [5] TXEMPTY 893 // 894 // Clear Transmit FIFO Empty event mask 895 // ENUMs: 896 // CLR Clear interrupt mask 897 // NOEFF Writing 0 has no effect 898 #define SPI_IMCLR_TXEMPTY 0x00000020U 899 #define SPI_IMCLR_TXEMPTY_M 0x00000020U 900 #define SPI_IMCLR_TXEMPTY_S 5U 901 #define SPI_IMCLR_TXEMPTY_CLR 0x00000020U 902 #define SPI_IMCLR_TXEMPTY_NOEFF 0x00000000U 903 904 // Field: [4] TX 905 // 906 // Clear Transmit FIFO event mask 907 // ENUMs: 908 // CLR Clear interrupt mask 909 // NOEFF Writing 0 has no effect 910 #define SPI_IMCLR_TX 0x00000010U 911 #define SPI_IMCLR_TX_M 0x00000010U 912 #define SPI_IMCLR_TX_S 4U 913 #define SPI_IMCLR_TX_CLR 0x00000010U 914 #define SPI_IMCLR_TX_NOEFF 0x00000000U 915 916 // Field: [3] RX 917 // 918 // Clear Receive FIFO event mask 919 // ENUMs: 920 // CLR Clear interrupt mask 921 // NOEFF Writing 0 has no effect 922 #define SPI_IMCLR_RX 0x00000008U 923 #define SPI_IMCLR_RX_M 0x00000008U 924 #define SPI_IMCLR_RX_S 3U 925 #define SPI_IMCLR_RX_CLR 0x00000008U 926 #define SPI_IMCLR_RX_NOEFF 0x00000000U 927 928 // Field: [2] RTOUT 929 // 930 // Clear SPI Receive Time-Out event mask 931 // ENUMs: 932 // CLR Clear interrupt mask 933 // NOEFF Writing 0 has no effect 934 #define SPI_IMCLR_RTOUT 0x00000004U 935 #define SPI_IMCLR_RTOUT_M 0x00000004U 936 #define SPI_IMCLR_RTOUT_S 2U 937 #define SPI_IMCLR_RTOUT_CLR 0x00000004U 938 #define SPI_IMCLR_RTOUT_NOEFF 0x00000000U 939 940 // Field: [1] PER 941 // 942 // Clear Parity error event mask 943 // ENUMs: 944 // CLR Clear interrupt mask 945 // NOEFF Writing 0 has no effect 946 #define SPI_IMCLR_PER 0x00000002U 947 #define SPI_IMCLR_PER_M 0x00000002U 948 #define SPI_IMCLR_PER_S 1U 949 #define SPI_IMCLR_PER_CLR 0x00000002U 950 #define SPI_IMCLR_PER_NOEFF 0x00000000U 951 952 // Field: [0] RXOVF 953 // 954 // Clear RXFIFO overflow event mask 955 // ENUMs: 956 // CLR Clear interrupt mask 957 // NOEFF Writing 0 has no effect 958 #define SPI_IMCLR_RXOVF 0x00000001U 959 #define SPI_IMCLR_RXOVF_M 0x00000001U 960 #define SPI_IMCLR_RXOVF_S 0U 961 #define SPI_IMCLR_RXOVF_CLR 0x00000001U 962 #define SPI_IMCLR_RXOVF_NOEFF 0x00000000U 963 964 //***************************************************************************** 965 // 966 // Register: SPI_O_EMU 967 // 968 //***************************************************************************** 969 // Field: [0] HALT 970 // 971 // Halt control 972 // ENUMs: 973 // STOP Freeze option. The IP freezes functionality when 974 // the core halted input is asserted, and resumes 975 // when it is deasserted. The freeze can either be 976 // immediate or after the IP has reached a 977 // boundary (end of word boundary, based on DSS 978 // configuration) from where it can resume without 979 // corruption. 980 // RUN Free run option. The IP ignores the state of the 981 // core halted input. 982 #define SPI_EMU_HALT 0x00000001U 983 #define SPI_EMU_HALT_M 0x00000001U 984 #define SPI_EMU_HALT_S 0U 985 #define SPI_EMU_HALT_STOP 0x00000001U 986 #define SPI_EMU_HALT_RUN 0x00000000U 987 988 //***************************************************************************** 989 // 990 // Register: SPI_O_CTL0 991 // 992 //***************************************************************************** 993 // Field: [17] IDLEPOCI 994 // 995 // The Idle value of POCI - when TXFIFO is empty and before data is written 996 // into TXFIFO - can be controlled by this field. 997 // ENUMs: 998 // IDLE_ONE POCI outputs idle value of '1' 999 // IDLE_ZERO POCI output idle value of '0' 1000 #define SPI_CTL0_IDLEPOCI 0x00020000U 1001 #define SPI_CTL0_IDLEPOCI_M 0x00020000U 1002 #define SPI_CTL0_IDLEPOCI_S 17U 1003 #define SPI_CTL0_IDLEPOCI_IDLE_ONE 0x00020000U 1004 #define SPI_CTL0_IDLEPOCI_IDLE_ZERO 0x00000000U 1005 1006 // Field: [16] GPCRCEN 1007 // 1008 // General purpose CRC enable. This bit enables transmit side CRC unit for 1009 // general purpose use by software when SPI is disabled (CTL1.EN = 0). This bit 1010 // must be 0 when SPI is enabled. 1011 // ENUMs: 1012 // EN Transmit side CRC unit is available for general 1013 // purpose software use 1014 // DIS Transmit side CRC unit is not available for 1015 // general purpose software use 1016 #define SPI_CTL0_GPCRCEN 0x00010000U 1017 #define SPI_CTL0_GPCRCEN_M 0x00010000U 1018 #define SPI_CTL0_GPCRCEN_S 16U 1019 #define SPI_CTL0_GPCRCEN_EN 0x00010000U 1020 #define SPI_CTL0_GPCRCEN_DIS 0x00000000U 1021 1022 // Field: [15] CRCPOLY 1023 // 1024 // CRC polynomial selection. 1025 // ENUMs: 1026 // SIZE16BIT Selects 16-bit CCITT CRC polynomial 1027 // SIZE8BIT Selects 8-bit CCITT CRC polynomial 1028 #define SPI_CTL0_CRCPOLY 0x00008000U 1029 #define SPI_CTL0_CRCPOLY_M 0x00008000U 1030 #define SPI_CTL0_CRCPOLY_S 15U 1031 #define SPI_CTL0_CRCPOLY_SIZE16BIT 0x00008000U 1032 #define SPI_CTL0_CRCPOLY_SIZE8BIT 0x00000000U 1033 1034 // Field: [14] AUTOCRC 1035 // 1036 // Auto insert CRC 1037 // ENUMs: 1038 // EN Insert CRC into TXFIFO upon TXFIFO underflow 1039 // DIS Do not insert CRC into TXFIFO upon TXFIFO 1040 // underflow 1041 #define SPI_CTL0_AUTOCRC 0x00004000U 1042 #define SPI_CTL0_AUTOCRC_M 0x00004000U 1043 #define SPI_CTL0_AUTOCRC_S 14U 1044 #define SPI_CTL0_AUTOCRC_EN 0x00004000U 1045 #define SPI_CTL0_AUTOCRC_DIS 0x00000000U 1046 1047 // Field: [13] CRCEND 1048 // 1049 // CRC16 Endianness 1050 // ENUMs: 1051 // CRC_END_LSB Auto-insertion of CRC16 is least-significant byte 1052 // first 1053 // CRC_END_MSB Auto-insertion of CRC16 is most-significant byte 1054 // first 1055 #define SPI_CTL0_CRCEND 0x00002000U 1056 #define SPI_CTL0_CRCEND_M 0x00002000U 1057 #define SPI_CTL0_CRCEND_S 13U 1058 #define SPI_CTL0_CRCEND_CRC_END_LSB 0x00002000U 1059 #define SPI_CTL0_CRCEND_CRC_END_MSB 0x00000000U 1060 1061 // Field: [12] CSCLR 1062 // 1063 // Clear shift register counter on CS inactive. 1064 // This bit is relevant only in the peripheral mode, when CTL1.MS=0. 1065 // ENUMs: 1066 // EN Enable automatic clear of shift register when CS 1067 // goes inactive. 1068 // DIS Disable automatic clear of shift register when CS 1069 // goes inactive. 1070 #define SPI_CTL0_CSCLR 0x00001000U 1071 #define SPI_CTL0_CSCLR_M 0x00001000U 1072 #define SPI_CTL0_CSCLR_S 12U 1073 #define SPI_CTL0_CSCLR_EN 0x00001000U 1074 #define SPI_CTL0_CSCLR_DIS 0x00000000U 1075 1076 // Field: [11] FIFORST 1077 // 1078 // This bit is used to reset transmit and receive FIFO pointers. This bit is 1079 // auto cleared once the FIFO pointer reset operation is completed. 1080 // ENUMs: 1081 // RST_TRIG Trigger FIFO pointers reset when written to 1. 1082 // RST_DONE FIFO pointers reset completed when 0 is read 1083 #define SPI_CTL0_FIFORST 0x00000800U 1084 #define SPI_CTL0_FIFORST_M 0x00000800U 1085 #define SPI_CTL0_FIFORST_S 11U 1086 #define SPI_CTL0_FIFORST_RST_TRIG 0x00000800U 1087 #define SPI_CTL0_FIFORST_RST_DONE 0x00000000U 1088 1089 // Field: [10] HWCSN 1090 // 1091 // Hardware controlled chip select (CS) value. When set CS is zero till TX FIFO 1092 // is empty, as in - 1093 // a. CS is de-asserted 1094 // b. All data bytes are transmitted 1095 // c. CS is asserted 1096 // ENUMs: 1097 // EN HWCSN Enable 1098 // DIS HWCSN Disable 1099 #define SPI_CTL0_HWCSN 0x00000400U 1100 #define SPI_CTL0_HWCSN_M 0x00000400U 1101 #define SPI_CTL0_HWCSN_S 10U 1102 #define SPI_CTL0_HWCSN_EN 0x00000400U 1103 #define SPI_CTL0_HWCSN_DIS 0x00000000U 1104 1105 // Field: [9] SPH 1106 // 1107 // SCLK phase (Motorola SPI frame format only). 1108 // This bit selects the clock edge that captures data and enables it to change 1109 // state. 1110 // It has the most impact on the first bit transmitted by either permitting or 1111 // not permitting a clock transition before the first data capture clock edge. 1112 // ENUMs: 1113 // SECOND Data is captured on the second clock edge 1114 // transition. 1115 // FIRST Data is captured on the first clock edge 1116 // transition. 1117 #define SPI_CTL0_SPH 0x00000200U 1118 #define SPI_CTL0_SPH_M 0x00000200U 1119 #define SPI_CTL0_SPH_S 9U 1120 #define SPI_CTL0_SPH_SECOND 0x00000200U 1121 #define SPI_CTL0_SPH_FIRST 0x00000000U 1122 1123 // Field: [8] SPO 1124 // 1125 // SCLK polarity (Motorola SPI frame format only). 1126 // ENUMs: 1127 // HI SPI produces a steady state HI value on the SCLK 1128 // LO SPI produces a steady state LO value on the SCLK 1129 #define SPI_CTL0_SPO 0x00000100U 1130 #define SPI_CTL0_SPO_M 0x00000100U 1131 #define SPI_CTL0_SPO_S 8U 1132 #define SPI_CTL0_SPO_HI 0x00000100U 1133 #define SPI_CTL0_SPO_LO 0x00000000U 1134 1135 // Field: [6:5] FRF 1136 // 1137 // Frame format select 1138 // ENUMs: 1139 // MICROWIRE MICROWIRE frame format 1140 // TI_SYNC TI synchronous serial frame format 1141 // MOTOROLA_4WIRE Motorola SPI frame format (4-wire mode) 1142 // MOTOROLA_3WIRE Motorola SPI frame format (3-wire mode) 1143 #define SPI_CTL0_FRF_W 2U 1144 #define SPI_CTL0_FRF_M 0x00000060U 1145 #define SPI_CTL0_FRF_S 5U 1146 #define SPI_CTL0_FRF_MICROWIRE 0x00000060U 1147 #define SPI_CTL0_FRF_TI_SYNC 0x00000040U 1148 #define SPI_CTL0_FRF_MOTOROLA_4WIRE 0x00000020U 1149 #define SPI_CTL0_FRF_MOTOROLA_3WIRE 0x00000000U 1150 1151 // Field: [3:0] DSS 1152 // 1153 // Data size select. The applicable DSS values for controller mode operation 1154 // are 0x3 to 0xF and for peripheral mode operation are 0x6 to 0xF. DSS values 1155 // 0x0 to 0x2 are reserved and must not be used. 1156 // ENUMs: 1157 // BITS_16 16-bits data size 1158 // BITS_15 15-bits data size 1159 // BITS_14 14-bits data size 1160 // BITS_13 13-bits data size 1161 // BITS_12 12-bits data size 1162 // BITS_11 11-bits data size 1163 // BITS_10 10-bits data size 1164 // BITS_9 9-bits data size 1165 // BITS_8 8-bits data size 1166 // BITS_7 7-bits data size 1167 // BITS_6 6-bits data size 1168 // BITS_5 5-bits data size 1169 // BITS_4 4-bits data size 1170 #define SPI_CTL0_DSS_W 4U 1171 #define SPI_CTL0_DSS_M 0x0000000FU 1172 #define SPI_CTL0_DSS_S 0U 1173 #define SPI_CTL0_DSS_BITS_16 0x0000000FU 1174 #define SPI_CTL0_DSS_BITS_15 0x0000000EU 1175 #define SPI_CTL0_DSS_BITS_14 0x0000000DU 1176 #define SPI_CTL0_DSS_BITS_13 0x0000000CU 1177 #define SPI_CTL0_DSS_BITS_12 0x0000000BU 1178 #define SPI_CTL0_DSS_BITS_11 0x0000000AU 1179 #define SPI_CTL0_DSS_BITS_10 0x00000009U 1180 #define SPI_CTL0_DSS_BITS_9 0x00000008U 1181 #define SPI_CTL0_DSS_BITS_8 0x00000007U 1182 #define SPI_CTL0_DSS_BITS_7 0x00000006U 1183 #define SPI_CTL0_DSS_BITS_6 0x00000005U 1184 #define SPI_CTL0_DSS_BITS_5 0x00000004U 1185 #define SPI_CTL0_DSS_BITS_4 0x00000003U 1186 1187 //***************************************************************************** 1188 // 1189 // Register: SPI_O_CTL1 1190 // 1191 //***************************************************************************** 1192 // Field: [29:24] RTOUT 1193 // 1194 // Receive Timeout (only for Peripheral mode) 1195 // Defines the number of CLKSVT clock cycles after which the Receive Timeout 1196 // flag RIS.RTOUT is set. 1197 // A value of 0 disables this function. 1198 #define SPI_CTL1_RTOUT_W 6U 1199 #define SPI_CTL1_RTOUT_M 0x3F000000U 1200 #define SPI_CTL1_RTOUT_S 24U 1201 1202 // Field: [23:16] REPTX 1203 // 1204 // Counter to repeat last transfer (only in controller mode) 1205 // 0: repeat last transfer is disabled. 1206 // x: repeat the last transfer with the provided value. 1207 // The transfer will be started with writing a data into the TX FIFO. Sending 1208 // the data will be repeated REPTX number of times, so the data will be 1209 // transferred x+1 times in total. 1210 // It can be used to clean a transfer or to pull a certain amount of data by a 1211 // peripheral. 1212 // ENUMs: 1213 // DIS REPTX disable 1214 #define SPI_CTL1_REPTX_W 8U 1215 #define SPI_CTL1_REPTX_M 0x00FF0000U 1216 #define SPI_CTL1_REPTX_S 16U 1217 #define SPI_CTL1_REPTX_DIS 0x00000000U 1218 1219 // Field: [15:12] CDMODE 1220 // 1221 // Command Data Mode. This bit field value determines the behavior of C/D or CS 1222 // signal when CDEN = 1. CS pin held low indicates command phase and CS pin 1223 // held high indicates data phase. 1224 // When CDMODE = 0x0, the CS pin is always held high during transfer indicating 1225 // data phase only operation (manual mode). 1226 // When CDMODE = 0xF, the CS pin is always held low during transfer indicating 1227 // command phase only operation (manual mode). 1228 // When CDMODE = 0x1 to 0xE, the CS pin is held low for the number of bytes 1229 // indicated by CDMODE value for the command phase and held high for the 1230 // remaining transfers in the data phase (automatic mode). 1231 // When CDMODE is set to value 0x1 to 0xE, reading CDMODE during operation 1232 // indicates the remaining bytes to be transferred in the command phase. 1233 // ENUMs: 1234 // COMMAND Manual mode: Command 1235 // DATA Manual mode: Data 1236 #define SPI_CTL1_CDMODE_W 4U 1237 #define SPI_CTL1_CDMODE_M 0x0000F000U 1238 #define SPI_CTL1_CDMODE_S 12U 1239 #define SPI_CTL1_CDMODE_COMMAND 0x0000F000U 1240 #define SPI_CTL1_CDMODE_DATA 0x00000000U 1241 1242 // Field: [11] CDEN 1243 // 1244 // Command/Data mode enable. This feature is applicable only in controller mode 1245 // and for 8-bit transfers (CTL0.DSS = 7). The chip select pin is used for 1246 // command/data signaling in Motorola SPI frame format (3-wire) operation. 1247 // ENUMs: 1248 // EN C/D Mode Enable 1249 // DIS C/D Mode Disable 1250 #define SPI_CTL1_CDEN 0x00000800U 1251 #define SPI_CTL1_CDEN_M 0x00000800U 1252 #define SPI_CTL1_CDEN_S 11U 1253 #define SPI_CTL1_CDEN_EN 0x00000800U 1254 #define SPI_CTL1_CDEN_DIS 0x00000000U 1255 1256 // Field: [7] PBS 1257 // 1258 // Parity bit select 1259 // ENUMs: 1260 // BIT1 Bit 1 is used for Parity, Bit 0 is ignored 1261 // BIT0 Bit 0 is used for Parity 1262 #define SPI_CTL1_PBS 0x00000080U 1263 #define SPI_CTL1_PBS_M 0x00000080U 1264 #define SPI_CTL1_PBS_S 7U 1265 #define SPI_CTL1_PBS_BIT1 0x00000080U 1266 #define SPI_CTL1_PBS_BIT0 0x00000000U 1267 1268 // Field: [6] PES 1269 // 1270 // Even parity select. 1271 // ENUMs: 1272 // EVEN Even Parity mode 1273 // ODD Odd Parity mode 1274 #define SPI_CTL1_PES 0x00000040U 1275 #define SPI_CTL1_PES_M 0x00000040U 1276 #define SPI_CTL1_PES_S 6U 1277 #define SPI_CTL1_PES_EVEN 0x00000040U 1278 #define SPI_CTL1_PES_ODD 0x00000000U 1279 1280 // Field: [5] PEN 1281 // 1282 // Parity enable. If enabled the last bit will be used as parity to evaluate 1283 // the correct reception of the previous bits. 1284 // In case of parity mismatch the parity error flag RIS.PER will be set. This 1285 // feature is available only in SPI controller mode. 1286 // ENUMs: 1287 // EN Enable Parity function 1288 // DIS Disable Parity function 1289 #define SPI_CTL1_PEN 0x00000020U 1290 #define SPI_CTL1_PEN_M 0x00000020U 1291 #define SPI_CTL1_PEN_S 5U 1292 #define SPI_CTL1_PEN_EN 0x00000020U 1293 #define SPI_CTL1_PEN_DIS 0x00000000U 1294 1295 // Field: [4] MSB 1296 // 1297 // MSB first select. Controls the direction of receive and transmit shift 1298 // register. MSB first configuration (MSB = 1) must be selected when CRC 1299 // feature is used for SPI communication. 1300 // ENUMs: 1301 // MSB MSB first 1302 // LSB LSB first 1303 #define SPI_CTL1_MSB 0x00000010U 1304 #define SPI_CTL1_MSB_M 0x00000010U 1305 #define SPI_CTL1_MSB_S 4U 1306 #define SPI_CTL1_MSB_MSB 0x00000010U 1307 #define SPI_CTL1_MSB_LSB 0x00000000U 1308 1309 // Field: [3] POD 1310 // 1311 // Peripheral data output disable. 1312 // This bit is relevant only in the peripheral mode, MS=1. In 1313 // multiple-peripheral systems, it is possible for a SPI controller to 1314 // broadcast a message to all peripherals in the system while ensuring that 1315 // only one peripheral drives data onto its serial output line. In such systems 1316 // the POCI lines from multiple peripherals could be tied together. To operate 1317 // in such systems, this bit field can be set if the SPI peripheral is not 1318 // supposed to drive the POCI output. 1319 // ENUMs: 1320 // EN SPI cannot drive the POCI output in peripheral 1321 // mode. 1322 // DIS SPI can drive the POCI output in peripheral mode. 1323 #define SPI_CTL1_POD 0x00000008U 1324 #define SPI_CTL1_POD_M 0x00000008U 1325 #define SPI_CTL1_POD_S 3U 1326 #define SPI_CTL1_POD_EN 0x00000008U 1327 #define SPI_CTL1_POD_DIS 0x00000000U 1328 1329 // Field: [2] MS 1330 // 1331 // Controller or peripheral mode select. This bit can be modified only when SPI 1332 // is disabled, CTL1.EN=0. 1333 // ENUMs: 1334 // CONTROLLER Select Controller mode 1335 // PERIPHERAL Select Peripheral mode 1336 #define SPI_CTL1_MS 0x00000004U 1337 #define SPI_CTL1_MS_M 0x00000004U 1338 #define SPI_CTL1_MS_S 2U 1339 #define SPI_CTL1_MS_CONTROLLER 0x00000004U 1340 #define SPI_CTL1_MS_PERIPHERAL 0x00000000U 1341 1342 // Field: [1] LBM 1343 // 1344 // Loop back mode control 1345 // ENUMs: 1346 // EN Enable loopback mode. Output of transmit serial 1347 // shifter is connected to input of receive serial 1348 // shifter internally. 1349 // DIS Disable loopback mode. Normal serial port 1350 // operation enabled. 1351 #define SPI_CTL1_LBM 0x00000002U 1352 #define SPI_CTL1_LBM_M 0x00000002U 1353 #define SPI_CTL1_LBM_S 1U 1354 #define SPI_CTL1_LBM_EN 0x00000002U 1355 #define SPI_CTL1_LBM_DIS 0x00000000U 1356 1357 // Field: [0] EN 1358 // 1359 // SPI enable. 1360 // NOTE: This bit field must be set to 1 using a separate write access, after 1361 // the other bit fields have been configured. 1362 // ENUMs: 1363 // EN SPI Enabled and released for operation. 1364 // DIS SPI is disabled 1365 #define SPI_CTL1_EN 0x00000001U 1366 #define SPI_CTL1_EN_M 0x00000001U 1367 #define SPI_CTL1_EN_S 0U 1368 #define SPI_CTL1_EN_EN 0x00000001U 1369 #define SPI_CTL1_EN_DIS 0x00000000U 1370 1371 //***************************************************************************** 1372 // 1373 // Register: SPI_O_CLKCFG0 1374 // 1375 //***************************************************************************** 1376 // Field: [2:0] PRESC 1377 // 1378 // Prescaler configuration 1379 // ENUMs: 1380 // DIV_BY_8 Divide clock source by 8 1381 // DIV_BY_7 Divide clock source by 7 1382 // DIV_BY_6 Divide clock source by 6 1383 // DIV_BY_5 Divide clock source by 5 1384 // DIV_BY_4 Divide clock source by 4 1385 // DIV_BY_3 Divide clock source by 3 1386 // DIV_BY_2 Divide clock source by 2 1387 // DIV_BY_1 Do not divide clock source 1388 #define SPI_CLKCFG0_PRESC_W 3U 1389 #define SPI_CLKCFG0_PRESC_M 0x00000007U 1390 #define SPI_CLKCFG0_PRESC_S 0U 1391 #define SPI_CLKCFG0_PRESC_DIV_BY_8 0x00000007U 1392 #define SPI_CLKCFG0_PRESC_DIV_BY_7 0x00000006U 1393 #define SPI_CLKCFG0_PRESC_DIV_BY_6 0x00000005U 1394 #define SPI_CLKCFG0_PRESC_DIV_BY_5 0x00000004U 1395 #define SPI_CLKCFG0_PRESC_DIV_BY_4 0x00000003U 1396 #define SPI_CLKCFG0_PRESC_DIV_BY_3 0x00000002U 1397 #define SPI_CLKCFG0_PRESC_DIV_BY_2 0x00000001U 1398 #define SPI_CLKCFG0_PRESC_DIV_BY_1 0x00000000U 1399 1400 //***************************************************************************** 1401 // 1402 // Register: SPI_O_CLKCFG1 1403 // 1404 //***************************************************************************** 1405 // Field: [19:16] DSAMPLE 1406 // 1407 // Delayed sampling. In controller mode the data on the POCI pin will be 1408 // delayed sampled by the defined CLKSVT clock cycles. DSAMPLE values can range 1409 // from 0 to SCR+1. Typically, values of 1 or 2 would suffice. 1410 #define SPI_CLKCFG1_DSAMPLE_W 4U 1411 #define SPI_CLKCFG1_DSAMPLE_M 0x000F0000U 1412 #define SPI_CLKCFG1_DSAMPLE_S 16U 1413 1414 // Field: [9:0] SCR 1415 // 1416 // Serial clock divider. This is used to generate the transmit and receive bit 1417 // rate of the SPI. 1418 // The SPI bit rate: (SPI functional clock frequency)/((SCR+1)*PRESC). SCR 1419 // value can be from 0 to 1023. 1420 #define SPI_CLKCFG1_SCR_W 10U 1421 #define SPI_CLKCFG1_SCR_M 0x000003FFU 1422 #define SPI_CLKCFG1_SCR_S 0U 1423 1424 //***************************************************************************** 1425 // 1426 // Register: SPI_O_IFLS 1427 // 1428 //***************************************************************************** 1429 // Field: [10:8] RXSEL 1430 // 1431 // Receive FIFO Level Select. The trigger points for the receive interrupt are 1432 // as follows: 1433 // ENUMs: 1434 // LEVEL_1 Trigger when RX FIFO contains >= 1 byte 1435 // LVL_RES6 Reserved 1436 // LVL_FULL RX FIFO is full 1437 // LVL_RES4 Reserved 1438 // LVL_3_4 RX FIFO >= 3/4 full 1439 // LVL_1_2 RX FIFO >= 1/2 full (default) 1440 // LVL_1_4 RX FIFO >= 1/4 full 1441 // LVL_OFF Reserved 1442 #define SPI_IFLS_RXSEL_W 3U 1443 #define SPI_IFLS_RXSEL_M 0x00000700U 1444 #define SPI_IFLS_RXSEL_S 8U 1445 #define SPI_IFLS_RXSEL_LEVEL_1 0x00000700U 1446 #define SPI_IFLS_RXSEL_LVL_RES6 0x00000600U 1447 #define SPI_IFLS_RXSEL_LVL_FULL 0x00000500U 1448 #define SPI_IFLS_RXSEL_LVL_RES4 0x00000400U 1449 #define SPI_IFLS_RXSEL_LVL_3_4 0x00000300U 1450 #define SPI_IFLS_RXSEL_LVL_1_2 0x00000200U 1451 #define SPI_IFLS_RXSEL_LVL_1_4 0x00000100U 1452 #define SPI_IFLS_RXSEL_LVL_OFF 0x00000000U 1453 1454 // Field: [2:0] TXSEL 1455 // 1456 // Transmit FIFO Level Select. The trigger points for the transmit interrupt 1457 // are as follows: 1458 // ENUMs: 1459 // LEVEL_1 Trigger when TX FIFO has >= 1 byte free 1460 // LVL_RES6 Reserved 1461 // LVL_EMPTY TX FIFO is empty 1462 // LVL_RES4 Reserved 1463 // LVL_1_4 TX FIFO <= 1/4 empty 1464 // LVL_1_2 TX FIFO <= 1/2 empty (default) 1465 // LVL_3_4 TX FIFO <= 3/4 empty 1466 // LVL_OFF Reserved 1467 #define SPI_IFLS_TXSEL_W 3U 1468 #define SPI_IFLS_TXSEL_M 0x00000007U 1469 #define SPI_IFLS_TXSEL_S 0U 1470 #define SPI_IFLS_TXSEL_LEVEL_1 0x00000007U 1471 #define SPI_IFLS_TXSEL_LVL_RES6 0x00000006U 1472 #define SPI_IFLS_TXSEL_LVL_EMPTY 0x00000005U 1473 #define SPI_IFLS_TXSEL_LVL_RES4 0x00000004U 1474 #define SPI_IFLS_TXSEL_LVL_1_4 0x00000003U 1475 #define SPI_IFLS_TXSEL_LVL_1_2 0x00000002U 1476 #define SPI_IFLS_TXSEL_LVL_3_4 0x00000001U 1477 #define SPI_IFLS_TXSEL_LVL_OFF 0x00000000U 1478 1479 //***************************************************************************** 1480 // 1481 // Register: SPI_O_DMACR 1482 // 1483 //***************************************************************************** 1484 // Field: [8] TXEN 1485 // 1486 // Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is 1487 // enabled. 1488 // ENUMs: 1489 // EN Enable TX DMA 1490 // DIS Disable TX DMA 1491 #define SPI_DMACR_TXEN 0x00000100U 1492 #define SPI_DMACR_TXEN_M 0x00000100U 1493 #define SPI_DMACR_TXEN_S 8U 1494 #define SPI_DMACR_TXEN_EN 0x00000100U 1495 #define SPI_DMACR_TXEN_DIS 0x00000000U 1496 1497 // Field: [0] RXEN 1498 // 1499 // Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is 1500 // enabled. 1501 // ENUMs: 1502 // EN Enable RX DMA 1503 // DIS Disable RX DMA 1504 #define SPI_DMACR_RXEN 0x00000001U 1505 #define SPI_DMACR_RXEN_M 0x00000001U 1506 #define SPI_DMACR_RXEN_S 0U 1507 #define SPI_DMACR_RXEN_EN 0x00000001U 1508 #define SPI_DMACR_RXEN_DIS 0x00000000U 1509 1510 //***************************************************************************** 1511 // 1512 // Register: SPI_O_RXCRC 1513 // 1514 //***************************************************************************** 1515 // Field: [15:0] DATA 1516 // 1517 // CRC value 1518 // SW should read RXCRC register at the end of data transmission to 1519 // reinitialize the seed value to all ones 1520 #define SPI_RXCRC_DATA_W 16U 1521 #define SPI_RXCRC_DATA_M 0x0000FFFFU 1522 #define SPI_RXCRC_DATA_S 0U 1523 1524 //***************************************************************************** 1525 // 1526 // Register: SPI_O_TXCRC 1527 // 1528 //***************************************************************************** 1529 // Field: [31] AUTOCRCINS 1530 // 1531 // Status to indicate if Auto CRC has been inserted into TXFIFO. 1532 // This is applicable only if CTL0.AUTOCRC enable bit is set. 1533 // SW should read TXCRC register to clear auto inserted CRC at the end of the 1534 // transfer. 1535 // ENUMs: 1536 // INS Auto CRC inserted 1537 // NOTINS Auto CRC not yet inserted 1538 #define SPI_TXCRC_AUTOCRCINS 0x80000000U 1539 #define SPI_TXCRC_AUTOCRCINS_M 0x80000000U 1540 #define SPI_TXCRC_AUTOCRCINS_S 31U 1541 #define SPI_TXCRC_AUTOCRCINS_INS 0x80000000U 1542 #define SPI_TXCRC_AUTOCRCINS_NOTINS 0x00000000U 1543 1544 // Field: [15:0] DATA 1545 // 1546 // CRC value 1547 #define SPI_TXCRC_DATA_W 16U 1548 #define SPI_TXCRC_DATA_M 0x0000FFFFU 1549 #define SPI_TXCRC_DATA_S 0U 1550 1551 //***************************************************************************** 1552 // 1553 // Register: SPI_O_TXFHDR32 1554 // 1555 //***************************************************************************** 1556 // Field: [31:0] DATA 1557 // 1558 // This field can be used to write four bytes of header data into the TXFIFO 1559 #define SPI_TXFHDR32_DATA_W 32U 1560 #define SPI_TXFHDR32_DATA_M 0xFFFFFFFFU 1561 #define SPI_TXFHDR32_DATA_S 0U 1562 1563 //***************************************************************************** 1564 // 1565 // Register: SPI_O_TXFHDR24 1566 // 1567 //***************************************************************************** 1568 // Field: [31:0] DATA 1569 // 1570 // This field can be used to write three bytes of header data into the TXFIFO. 1571 #define SPI_TXFHDR24_DATA_W 32U 1572 #define SPI_TXFHDR24_DATA_M 0xFFFFFFFFU 1573 #define SPI_TXFHDR24_DATA_S 0U 1574 1575 //***************************************************************************** 1576 // 1577 // Register: SPI_O_TXFHDR16 1578 // 1579 //***************************************************************************** 1580 // Field: [31:0] DATA 1581 // 1582 // This field can be used to write two bytes of header data into the TXFIFO. 1583 #define SPI_TXFHDR16_DATA_W 32U 1584 #define SPI_TXFHDR16_DATA_M 0xFFFFFFFFU 1585 #define SPI_TXFHDR16_DATA_S 0U 1586 1587 //***************************************************************************** 1588 // 1589 // Register: SPI_O_TXFHDR8 1590 // 1591 //***************************************************************************** 1592 // Field: [31:0] DATA 1593 // 1594 // This field can be used to write one byte of header data into the TXFIFO. 1595 #define SPI_TXFHDR8_DATA_W 32U 1596 #define SPI_TXFHDR8_DATA_M 0xFFFFFFFFU 1597 #define SPI_TXFHDR8_DATA_S 0U 1598 1599 //***************************************************************************** 1600 // 1601 // Register: SPI_O_TXFHDRC 1602 // 1603 //***************************************************************************** 1604 // Field: [3] CSGATE 1605 // 1606 // Chip Select Gating control register. If this bit is set, header update 1607 // register writes are blocked when chip select (CS) is active low, and HDRIGN 1608 // bit is set. 1609 // This bit resets to 0. 1610 // ENUMs: 1611 // BLK Header update register writes are blocked when CS 1612 // is active (low) 1613 // UNBLK The first header update register write is not 1614 // blocked based on CS active status (low). 1615 // If no header update 1616 // occurred when CS was high (inactive), the first 1617 // header update is allowed when CS is low 1618 // (active), and the HDRCMT bit is set. The use 1619 // case is for the external controller to ensure 1620 // that the SCLK is not driven during this header 1621 // update. 1622 // If the header is already 1623 // updated when CS is high and inactive, HDRCMT is 1624 // set immediately when CS drops to active low 1625 // state, and header writes when CS is low are 1626 // ignored even if this UNBLK bit is set. 1627 #define SPI_TXFHDRC_CSGATE 0x00000008U 1628 #define SPI_TXFHDRC_CSGATE_M 0x00000008U 1629 #define SPI_TXFHDRC_CSGATE_S 3U 1630 #define SPI_TXFHDRC_CSGATE_BLK 0x00000008U 1631 #define SPI_TXFHDRC_CSGATE_UNBLK 0x00000000U 1632 1633 // Field: [2] HDRCMT 1634 // 1635 // Header Committed field. This bit is set when the HDREN bit is set and CS is 1636 // sampled low. This bit remains 0 otherwise. When set, this bit can be written 1637 // to a value of 0 to clear. 1638 // ENUMs: 1639 // SET Header update is committed 1640 // CLR Header update is not committed 1641 #define SPI_TXFHDRC_HDRCMT 0x00000004U 1642 #define SPI_TXFHDRC_HDRCMT_M 0x00000004U 1643 #define SPI_TXFHDRC_HDRCMT_S 2U 1644 #define SPI_TXFHDRC_HDRCMT_SET 0x00000004U 1645 #define SPI_TXFHDRC_HDRCMT_CLR 0x00000000U 1646 1647 // Field: [1] HDRIGN 1648 // 1649 // Header Ignored field. When CSGATE is set to BLK, this bit is set when the 1650 // last Header update register TXFHDRn is written when CS is low or HDRCMT is 1651 // already set. When CSGATE is set to UNBLK, this bit is set only when the 1652 // header update register is written when HDRCMT is already set. This bit 1653 // remains 0 otherwise. When set, this bit can be written to a value of 0 to 1654 // clear. 1655 // ENUMs: 1656 // SET Header update is ignored 1657 // CLR Header update is not ignored 1658 #define SPI_TXFHDRC_HDRIGN 0x00000002U 1659 #define SPI_TXFHDRC_HDRIGN_M 0x00000002U 1660 #define SPI_TXFHDRC_HDRIGN_S 1U 1661 #define SPI_TXFHDRC_HDRIGN_SET 0x00000002U 1662 #define SPI_TXFHDRC_HDRIGN_CLR 0x00000000U 1663 1664 // Field: [0] HDREN 1665 // 1666 // Header enable field. When CSGATE is set to BLK, this bit has to be set by 1667 // software to enable atomic header feature. When CSGATE is set to UNBLK, this 1668 // field is set automatically whenever a write to header update registers 1669 // TXFHDRn occurs. 1670 // ENUMs: 1671 // EN Atomic header update feature enable 1672 // DIS Atomic header update feature disable 1673 #define SPI_TXFHDRC_HDREN 0x00000001U 1674 #define SPI_TXFHDRC_HDREN_M 0x00000001U 1675 #define SPI_TXFHDRC_HDREN_S 0U 1676 #define SPI_TXFHDRC_HDREN_EN 0x00000001U 1677 #define SPI_TXFHDRC_HDREN_DIS 0x00000000U 1678 1679 //***************************************************************************** 1680 // 1681 // Register: SPI_O_RXDATA 1682 // 1683 //***************************************************************************** 1684 // Field: [15:0] DATA 1685 // 1686 // Received Data. When read, the entry in the receive FIFO, pointed to by the 1687 // current FIFO read pointer is accessed. As data values are read by the 1688 // receive logic from the incoming data frame, they are placed into the entry 1689 // in the receive FIFO, pointed to by the current RX FIFO write pointer. 1690 // Received data less than 16 bits is automatically right-justified in the 1691 // receive buffer. 1692 #define SPI_RXDATA_DATA_W 16U 1693 #define SPI_RXDATA_DATA_M 0x0000FFFFU 1694 #define SPI_RXDATA_DATA_S 0U 1695 1696 //***************************************************************************** 1697 // 1698 // Register: SPI_O_TXDATA 1699 // 1700 //***************************************************************************** 1701 // Field: [15:0] DATA 1702 // 1703 // Transmit Data. When read, the last entry in the transmit FIFO, pointed to by 1704 // the current FIFO write pointer is accessed. 1705 // When written, the entry in the TX FIFO pointed to by the write pointer, is 1706 // written to. Data values are read from the transmit FIFO by the transmit 1707 // logic. It is loaded into the transmit serial shifter, then serially shifted 1708 // out onto the output pin at the programmed bit rate. 1709 // When a data size of less than 16 bits is selected, the user must 1710 // right-justify data written to the transmit FIFO. The transmit logic ignores 1711 // the unused bits. 1712 #define SPI_TXDATA_DATA_W 16U 1713 #define SPI_TXDATA_DATA_M 0x0000FFFFU 1714 #define SPI_TXDATA_DATA_S 0U 1715 1716 //***************************************************************************** 1717 // 1718 // Register: SPI_O_STA 1719 // 1720 //***************************************************************************** 1721 // Field: [13:8] TXFIFOLVL 1722 // 1723 // Indicates how many locations of TXFIFO are currently filled with data 1724 #define SPI_STA_TXFIFOLVL_W 6U 1725 #define SPI_STA_TXFIFOLVL_M 0x00003F00U 1726 #define SPI_STA_TXFIFOLVL_S 8U 1727 1728 // Field: [6] TXDONE 1729 // 1730 // Transmit done. Indicates whether the last bit has left the Shift register 1731 // after a transmission 1732 // ENUMs: 1733 // TX_DONE Last bit has been shifted out, and the 1734 // transmission is done 1735 // TX_ONGOING Last bit has not yet left the Shift register, and 1736 // the transmission is ongoing. 1737 #define SPI_STA_TXDONE 0x00000040U 1738 #define SPI_STA_TXDONE_M 0x00000040U 1739 #define SPI_STA_TXDONE_S 6U 1740 #define SPI_STA_TXDONE_TX_DONE 0x00000040U 1741 #define SPI_STA_TXDONE_TX_ONGOING 0x00000000U 1742 1743 // Field: [5] CSD 1744 // 1745 // Detection of CS deassertion in the middle of a data frame transmission 1746 // results in this error being set. This feature is only available in the 1747 // peripheral mode. 1748 // ENUMs: 1749 // ERR An error is generated when CS posedge 1750 // (deassertion) is detected before the entire 1751 // data frame is transmitted. 1752 // NOERR No CS posedge is detected before the entire data 1753 // frame has been transmitted. 1754 #define SPI_STA_CSD 0x00000020U 1755 #define SPI_STA_CSD_M 0x00000020U 1756 #define SPI_STA_CSD_S 5U 1757 #define SPI_STA_CSD_ERR 0x00000020U 1758 #define SPI_STA_CSD_NOERR 0x00000000U 1759 1760 // Field: [4] BUSY 1761 // 1762 // SPI Busy status 1763 // ENUMs: 1764 // ACTIVE SPI is currently transmitting and/or receiving 1765 // data, or transmit FIFO is not empty. 1766 // IDLE SPI is in idle mode. 1767 #define SPI_STA_BUSY 0x00000010U 1768 #define SPI_STA_BUSY_M 0x00000010U 1769 #define SPI_STA_BUSY_S 4U 1770 #define SPI_STA_BUSY_ACTIVE 0x00000010U 1771 #define SPI_STA_BUSY_IDLE 0x00000000U 1772 1773 // Field: [3] RNF 1774 // 1775 // Receive FIFO not full status. 1776 // ENUMs: 1777 // NOT_FULL Receive FIFO is not full. 1778 // FULL Receive FIFO is full. 1779 #define SPI_STA_RNF 0x00000008U 1780 #define SPI_STA_RNF_M 0x00000008U 1781 #define SPI_STA_RNF_S 3U 1782 #define SPI_STA_RNF_NOT_FULL 0x00000008U 1783 #define SPI_STA_RNF_FULL 0x00000000U 1784 1785 // Field: [2] RFE 1786 // 1787 // Receive FIFO empty status. 1788 // ENUMs: 1789 // EMPTY Receive FIFO is empty. 1790 // NOT_EMPTY Receive FIFO is not empty. 1791 #define SPI_STA_RFE 0x00000004U 1792 #define SPI_STA_RFE_M 0x00000004U 1793 #define SPI_STA_RFE_S 2U 1794 #define SPI_STA_RFE_EMPTY 0x00000004U 1795 #define SPI_STA_RFE_NOT_EMPTY 0x00000000U 1796 1797 // Field: [1] TNF 1798 // 1799 // Transmit FIFO not full status. 1800 // ENUMs: 1801 // NOT_FULL Transmit FIFO is not full. 1802 // FULL Transmit FIFO is full. 1803 #define SPI_STA_TNF 0x00000002U 1804 #define SPI_STA_TNF_M 0x00000002U 1805 #define SPI_STA_TNF_S 1U 1806 #define SPI_STA_TNF_NOT_FULL 0x00000002U 1807 #define SPI_STA_TNF_FULL 0x00000000U 1808 1809 // Field: [0] TFE 1810 // 1811 // Transmit FIFO empty status. 1812 // ENUMs: 1813 // EMPTY Transmit FIFO is empty. 1814 // NOT_EMPTY Transmit FIFO is not empty. 1815 #define SPI_STA_TFE 0x00000001U 1816 #define SPI_STA_TFE_M 0x00000001U 1817 #define SPI_STA_TFE_S 0U 1818 #define SPI_STA_TFE_EMPTY 0x00000001U 1819 #define SPI_STA_TFE_NOT_EMPTY 0x00000000U 1820 1821 1822 #endif // __SPI__ 1823
