1 /****************************************************************************** 2 * Filename: hw_rtc_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_RTC_H__ 34 #define __HW_RTC_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // RTC component 40 // 41 //***************************************************************************** 42 // Module Description 43 #define RTC_O_DESC 0x00000000U 44 45 // RTC control Register 46 #define RTC_O_CTL 0x00000004U 47 48 // Channel Arming Set 49 #define RTC_O_ARMSET 0x00000008U 50 51 // Channel Arming Clear 52 #define RTC_O_ARMCLR 0x0000000CU 53 54 // RTC Lower Time Slice 55 #define RTC_O_TIME8U 0x00000018U 56 57 // RTC Upper Time Slice 58 #define RTC_O_TIME524M 0x0000001CU 59 60 // Channel0 compare value 61 #define RTC_O_CH0CC8U 0x00000028U 62 63 // Channel1 capture Value 64 #define RTC_O_CH1CC8U 0x00000038U 65 66 // channel1 Input Configuration 67 #define RTC_O_CH1CFG 0x0000003CU 68 69 // Interrupt mask 70 #define RTC_O_IMASK 0x00000044U 71 72 // Raw interrupt status 73 #define RTC_O_RIS 0x00000048U 74 75 // Masked interrupt status 76 #define RTC_O_MIS 0x0000004CU 77 78 // Interrupt set 79 #define RTC_O_ISET 0x00000050U 80 81 // Interrupt clear 82 #define RTC_O_ICLR 0x00000054U 83 84 // Interrupt mask set 85 #define RTC_O_IMSET 0x00000058U 86 87 // Interrupt clear 88 #define RTC_O_IMCLR 0x0000005CU 89 90 // Emulation 91 #define RTC_O_EMU 0x00000060U 92 93 //***************************************************************************** 94 // 95 // Register: RTC_O_DESC 96 // 97 //***************************************************************************** 98 // Field: [31:16] MODID 99 // 100 // Module identifier used to uniquely identify this IP. 101 #define RTC_DESC_MODID_W 16U 102 #define RTC_DESC_MODID_M 0xFFFF0000U 103 #define RTC_DESC_MODID_S 16U 104 105 // Field: [15:12] STDIPOFF 106 // 107 // Standard IP MMR block offset. Standard IP MMRs are the set of from 108 // aggregated IRQ registers till DTB. 109 // 110 // 0: Standard IP MMRs do not exist 111 // 112 // 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP 113 // address) 114 #define RTC_DESC_STDIPOFF_W 4U 115 #define RTC_DESC_STDIPOFF_M 0x0000F000U 116 #define RTC_DESC_STDIPOFF_S 12U 117 118 // Field: [11:8] INSTIDX 119 // 120 // IP Instance ID number. If multiple instances of IP exist in the device, this 121 // field can identify the instance number (0-15). 122 #define RTC_DESC_INSTIDX_W 4U 123 #define RTC_DESC_INSTIDX_M 0x00000F00U 124 #define RTC_DESC_INSTIDX_S 8U 125 126 // Field: [7:4] MAJREV 127 // 128 // Major revision of IP (0-15). 129 #define RTC_DESC_MAJREV_W 4U 130 #define RTC_DESC_MAJREV_M 0x000000F0U 131 #define RTC_DESC_MAJREV_S 4U 132 133 // Field: [3:0] MINREV 134 // 135 // Minor revision of IP (0-15). 136 #define RTC_DESC_MINREV_W 4U 137 #define RTC_DESC_MINREV_M 0x0000000FU 138 #define RTC_DESC_MINREV_S 0U 139 140 //***************************************************************************** 141 // 142 // Register: RTC_O_CTL 143 // 144 //***************************************************************************** 145 // Field: [0] RST 146 // 147 // RTC counter reset. Writing 1 to this bit will reset the RTC counter, and 148 // cause it to resume counting from 0x0 149 // ENUMs: 150 // CLR Reset the timer. 151 // NOEFF No effect 152 #define RTC_CTL_RST 0x00000001U 153 #define RTC_CTL_RST_M 0x00000001U 154 #define RTC_CTL_RST_S 0U 155 #define RTC_CTL_RST_CLR 0x00000001U 156 #define RTC_CTL_RST_NOEFF 0x00000000U 157 158 //***************************************************************************** 159 // 160 // Register: RTC_O_ARMSET 161 // 162 //***************************************************************************** 163 // Field: [1] CH1 164 // 165 // Arming Channel 1 for capture operation. 166 // ENUMs: 167 // SET Enable the Channel 1 for capture operation 168 // NOEFF No effect on the channel 169 #define RTC_ARMSET_CH1 0x00000002U 170 #define RTC_ARMSET_CH1_M 0x00000002U 171 #define RTC_ARMSET_CH1_S 1U 172 #define RTC_ARMSET_CH1_SET 0x00000002U 173 #define RTC_ARMSET_CH1_NOEFF 0x00000000U 174 175 // Field: [0] CH0 176 // 177 // No effect on arming the channel. Read will give the status of the Channel 0. 178 // ENUMs: 179 // SET No effect on the compare channel 180 // NOEFF No effect on the channel 181 #define RTC_ARMSET_CH0 0x00000001U 182 #define RTC_ARMSET_CH0_M 0x00000001U 183 #define RTC_ARMSET_CH0_S 0U 184 #define RTC_ARMSET_CH0_SET 0x00000001U 185 #define RTC_ARMSET_CH0_NOEFF 0x00000000U 186 187 //***************************************************************************** 188 // 189 // Register: RTC_O_ARMCLR 190 // 191 //***************************************************************************** 192 // Field: [1] CH1 193 // 194 // Disarming Channel 1 195 // ENUMs: 196 // CLR Set channel in UNARMED state without triggering 197 // event unless a capture event happens in the 198 // same cycle 199 // NOEFF No effect on the channel 200 #define RTC_ARMCLR_CH1 0x00000002U 201 #define RTC_ARMCLR_CH1_M 0x00000002U 202 #define RTC_ARMCLR_CH1_S 1U 203 #define RTC_ARMCLR_CH1_CLR 0x00000002U 204 #define RTC_ARMCLR_CH1_NOEFF 0x00000000U 205 206 // Field: [0] CH0 207 // 208 // Disarming Channel 0 209 // ENUMs: 210 // CLR Set channel in UNARMED state without triggering 211 // event unless a compare event happens in the 212 // same cycle 213 // NOEFF No effect on the channel 214 #define RTC_ARMCLR_CH0 0x00000001U 215 #define RTC_ARMCLR_CH0_M 0x00000001U 216 #define RTC_ARMCLR_CH0_S 0U 217 #define RTC_ARMCLR_CH0_CLR 0x00000001U 218 #define RTC_ARMCLR_CH0_NOEFF 0x00000000U 219 220 //***************************************************************************** 221 // 222 // Register: RTC_O_TIME8U 223 // 224 //***************************************************************************** 225 // Field: [31:0] VAL 226 // 227 // Unsigned integer representing [34:3]slice of real time counter. 228 #define RTC_TIME8U_VAL_W 32U 229 #define RTC_TIME8U_VAL_M 0xFFFFFFFFU 230 #define RTC_TIME8U_VAL_S 0U 231 232 //***************************************************************************** 233 // 234 // Register: RTC_O_TIME524M 235 // 236 //***************************************************************************** 237 // Field: [31:0] VAL 238 // 239 // Unsigned integer representing. [50:19]slice of real time counter. 240 #define RTC_TIME524M_VAL_W 32U 241 #define RTC_TIME524M_VAL_M 0xFFFFFFFFU 242 #define RTC_TIME524M_VAL_S 0U 243 244 //***************************************************************************** 245 // 246 // Register: RTC_O_CH0CC8U 247 // 248 //***************************************************************************** 249 // Field: [31:0] VAL 250 // 251 // RTC Channel 0 compare value. This value is compared against TIME8U.VAL. A 252 // Channel 0 event is generated when TIME8U.VAL value reaches or exceeds this 253 // compare value. 254 #define RTC_CH0CC8U_VAL_W 32U 255 #define RTC_CH0CC8U_VAL_M 0xFFFFFFFFU 256 #define RTC_CH0CC8U_VAL_S 0U 257 258 //***************************************************************************** 259 // 260 // Register: RTC_O_CH1CC8U 261 // 262 //***************************************************************************** 263 // Field: [20:0] VAL 264 // 265 // TIME8U.VAL captured value at the last selected edge of capture event. 266 #define RTC_CH1CC8U_VAL_W 21U 267 #define RTC_CH1CC8U_VAL_M 0x001FFFFFU 268 #define RTC_CH1CC8U_VAL_S 0U 269 270 //***************************************************************************** 271 // 272 // Register: RTC_O_CH1CFG 273 // 274 //***************************************************************************** 275 // Field: [0] EDGE 276 // 277 // Edge detect configuration for capture source 278 // ENUMs: 279 // FALL Falling Edge. 280 // RISE Rising Edge. 281 #define RTC_CH1CFG_EDGE 0x00000001U 282 #define RTC_CH1CFG_EDGE_M 0x00000001U 283 #define RTC_CH1CFG_EDGE_S 0U 284 #define RTC_CH1CFG_EDGE_FALL 0x00000001U 285 #define RTC_CH1CFG_EDGE_RISE 0x00000000U 286 287 //***************************************************************************** 288 // 289 // Register: RTC_O_IMASK 290 // 291 //***************************************************************************** 292 // Field: [1] EV1 293 // 294 // Channel 1 Event Interrupt Mask. 295 // ENUMs: 296 // EN Enable Interrrupt Mask 297 // DIS Clear Interrupt Mask 298 #define RTC_IMASK_EV1 0x00000002U 299 #define RTC_IMASK_EV1_M 0x00000002U 300 #define RTC_IMASK_EV1_S 1U 301 #define RTC_IMASK_EV1_EN 0x00000002U 302 #define RTC_IMASK_EV1_DIS 0x00000000U 303 304 // Field: [0] EV0 305 // 306 // Channel 0 Event Interrupt Mask. 307 // ENUMs: 308 // EN Enable Interrrupt Mask 309 // DIS Disable Interrupt Mask 310 #define RTC_IMASK_EV0 0x00000001U 311 #define RTC_IMASK_EV0_M 0x00000001U 312 #define RTC_IMASK_EV0_S 0U 313 #define RTC_IMASK_EV0_EN 0x00000001U 314 #define RTC_IMASK_EV0_DIS 0x00000000U 315 316 //***************************************************************************** 317 // 318 // Register: RTC_O_RIS 319 // 320 //***************************************************************************** 321 // Field: [1] EV1 322 // 323 // Raw interrupt status for Channel 1 event. 324 // This bit is set to 1 when a capture event is received on Channel 1. 325 // This bit will be cleared when the bit in ICLR.EV1 is set to 1 or when the 326 // captured time value is read from the CH1CC8U register. 327 // ENUMs: 328 // SET Interrupt occured 329 // CLR Interrupt did not occur 330 #define RTC_RIS_EV1 0x00000002U 331 #define RTC_RIS_EV1_M 0x00000002U 332 #define RTC_RIS_EV1_S 1U 333 #define RTC_RIS_EV1_SET 0x00000002U 334 #define RTC_RIS_EV1_CLR 0x00000000U 335 336 // Field: [0] EV0 337 // 338 // Raw interrupt status for Channel 0 event. 339 // This bit is set to 1 when a compare event occurs on Channel 0. 340 // This bit will be cleared. When the corresponding bit in ICLR.EV0 is set to 341 // 1. Or when a new compare value is written in CH0CC8U register 342 // ENUMs: 343 // SET Interrupt occured 344 // CLR Interrupt did not occur 345 #define RTC_RIS_EV0 0x00000001U 346 #define RTC_RIS_EV0_M 0x00000001U 347 #define RTC_RIS_EV0_S 0U 348 #define RTC_RIS_EV0_SET 0x00000001U 349 #define RTC_RIS_EV0_CLR 0x00000000U 350 351 //***************************************************************************** 352 // 353 // Register: RTC_O_MIS 354 // 355 //***************************************************************************** 356 // Field: [1] EV1 357 // 358 // Masked interrupt status for channel 1 event. 359 // ENUMs: 360 // SET Interrupt occured 361 // CLR Interrupt did not occur 362 #define RTC_MIS_EV1 0x00000002U 363 #define RTC_MIS_EV1_M 0x00000002U 364 #define RTC_MIS_EV1_S 1U 365 #define RTC_MIS_EV1_SET 0x00000002U 366 #define RTC_MIS_EV1_CLR 0x00000000U 367 368 // Field: [0] EV0 369 // 370 // Masked interrupt status for channel 0 event. 371 // ENUMs: 372 // SET Interrupt occured 373 // CLR Interrupt did not occur 374 #define RTC_MIS_EV0 0x00000001U 375 #define RTC_MIS_EV0_M 0x00000001U 376 #define RTC_MIS_EV0_S 0U 377 #define RTC_MIS_EV0_SET 0x00000001U 378 #define RTC_MIS_EV0_CLR 0x00000000U 379 380 //***************************************************************************** 381 // 382 // Register: RTC_O_ISET 383 // 384 //***************************************************************************** 385 // Field: [1] EV1 386 // 387 // Set Channel 1 event Interrupt. 388 // ENUMs: 389 // SET Set interrupt 390 // NO_EFFECT Writing 0 has no effect 391 #define RTC_ISET_EV1 0x00000002U 392 #define RTC_ISET_EV1_M 0x00000002U 393 #define RTC_ISET_EV1_S 1U 394 #define RTC_ISET_EV1_SET 0x00000002U 395 #define RTC_ISET_EV1_NO_EFFECT 0x00000000U 396 397 // Field: [0] EV0 398 // 399 // Set Channel 0 event Interrupt. 400 // ENUMs: 401 // SET Set interrupt 402 // NO_EFFECT Writing 0 has no effect 403 #define RTC_ISET_EV0 0x00000001U 404 #define RTC_ISET_EV0_M 0x00000001U 405 #define RTC_ISET_EV0_S 0U 406 #define RTC_ISET_EV0_SET 0x00000001U 407 #define RTC_ISET_EV0_NO_EFFECT 0x00000000U 408 409 //***************************************************************************** 410 // 411 // Register: RTC_O_ICLR 412 // 413 //***************************************************************************** 414 // Field: [1] EV1 415 // 416 // Clears channel 1 event interrupt. 417 // ENUMs: 418 // CLR Clear Interrupt 419 // NO_EFF Writing 0 has no effect 420 #define RTC_ICLR_EV1 0x00000002U 421 #define RTC_ICLR_EV1_M 0x00000002U 422 #define RTC_ICLR_EV1_S 1U 423 #define RTC_ICLR_EV1_CLR 0x00000002U 424 #define RTC_ICLR_EV1_NO_EFF 0x00000000U 425 426 // Field: [0] EV0 427 // 428 // Clears channel 0 event interrupt. 429 // ENUMs: 430 // CLR Clear Interrupt. 431 // NO_EFF Writing 0 has no effect 432 #define RTC_ICLR_EV0 0x00000001U 433 #define RTC_ICLR_EV0_M 0x00000001U 434 #define RTC_ICLR_EV0_S 0U 435 #define RTC_ICLR_EV0_CLR 0x00000001U 436 #define RTC_ICLR_EV0_NO_EFF 0x00000000U 437 438 //***************************************************************************** 439 // 440 // Register: RTC_O_IMSET 441 // 442 //***************************************************************************** 443 // Field: [1] EV1 444 // 445 // Set channel 1 event interrupt mask. 446 // ENUMs: 447 // SET Set interrupt mask 448 // NO_EFF Writing 0 has no effect 449 #define RTC_IMSET_EV1 0x00000002U 450 #define RTC_IMSET_EV1_M 0x00000002U 451 #define RTC_IMSET_EV1_S 1U 452 #define RTC_IMSET_EV1_SET 0x00000002U 453 #define RTC_IMSET_EV1_NO_EFF 0x00000000U 454 455 // Field: [0] EV0 456 // 457 // Set channel 0 event interrupt mask. 458 // ENUMs: 459 // SET Set interrupt mask 460 // NO_EFF Writing 0 has no effect 461 #define RTC_IMSET_EV0 0x00000001U 462 #define RTC_IMSET_EV0_M 0x00000001U 463 #define RTC_IMSET_EV0_S 0U 464 #define RTC_IMSET_EV0_SET 0x00000001U 465 #define RTC_IMSET_EV0_NO_EFF 0x00000000U 466 467 //***************************************************************************** 468 // 469 // Register: RTC_O_IMCLR 470 // 471 //***************************************************************************** 472 // Field: [1] EV1 473 // 474 // Clears Channel 1 event interrupt mask. 475 // ENUMs: 476 // CLR Clear Interrupt Mask 477 // NO_EFF Writing 0 has no effect 478 #define RTC_IMCLR_EV1 0x00000002U 479 #define RTC_IMCLR_EV1_M 0x00000002U 480 #define RTC_IMCLR_EV1_S 1U 481 #define RTC_IMCLR_EV1_CLR 0x00000002U 482 #define RTC_IMCLR_EV1_NO_EFF 0x00000000U 483 484 // Field: [0] EV0 485 // 486 // Clears Channel 0 event interrupt mask. 487 // ENUMs: 488 // CLR Clear Interrupt Mask 489 // NO_EFF Writing 0 has no effect 490 #define RTC_IMCLR_EV0 0x00000001U 491 #define RTC_IMCLR_EV0_M 0x00000001U 492 #define RTC_IMCLR_EV0_S 0U 493 #define RTC_IMCLR_EV0_CLR 0x00000001U 494 #define RTC_IMCLR_EV0_NO_EFF 0x00000000U 495 496 //***************************************************************************** 497 // 498 // Register: RTC_O_EMU 499 // 500 //***************************************************************************** 501 // Field: [0] HALT 502 // 503 // Halt control. 504 // ENUMs: 505 // STOP Freeze option. The IP freezes functionality when 506 // the core halted input is asserted, and resumes 507 // when it is deasserted. The freeze can either be 508 // immediate or after the IP has reached a 509 // boundary from where it can resume without 510 // corruption. 511 // RUN Free run option. The IP ignores the state of the 512 // core halted input. 513 #define RTC_EMU_HALT 0x00000001U 514 #define RTC_EMU_HALT_M 0x00000001U 515 #define RTC_EMU_HALT_S 0U 516 #define RTC_EMU_HALT_STOP 0x00000001U 517 #define RTC_EMU_HALT_RUN 0x00000000U 518 519 520 #endif // __RTC__ 521
