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Searched refs:PRCM_BASE (Results 1 – 17 of 17) sorted by relevance

/hal_ti-latest/simplelink/source/ti/devices/cc13x2x7_cc26x2x7/driverlib/
Dprcm.c94 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPTCLKGR), // Index 0
95 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_SSICLKGR), // Index 1
96 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_UARTCLKGR), // Index 2
97 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2CCLKGR), // Index 3
98 (PRCM_BASE + PRCM_O_SECDMACLKGR), // Index 4
99 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPIOCLKGR), // Index 5
100 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_I2SCLKGR) // Index 6
106 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPTCLKGS), // Index 0
107 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_SSICLKGS), // Index 1
108 (PRCM_BASE + NONSECURE_OFFSET + PRCM_O_UARTCLKGS), // Index 2
[all …]
Dprcm.h334 HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_VDCTL) = ui32Enable; in PRCMMcuUldoConfigure()
373 HWREG( PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPTCLKDIV ) = clkDiv; in PRCMGPTimerClockDivisionSet()
399 return ( HWREG( PRCM_BASE + NONSECURE_OFFSET + PRCM_O_GPTCLKDIV )); in PRCMGPTimerClockDivisionGet()
416 HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 1; in PRCMAudioClockEnable()
432 HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 0; in PRCMAudioClockDisable()
608 return ((HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ? in PRCMLoadGet()
642 HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_RFCCLKG) = PRCM_RFCCLKG_CLK_EN; in PRCMDomainEnable()
646 HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_VIMSCLKG) = PRCM_VIMSCLKG_CLK_EN_M; in PRCMDomainEnable()
681 HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_RFCCLKG) = 0x0; in PRCMDomainDisable()
685 HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_VIMSCLKG) = 0x0; in PRCMDomainDisable()
[all …]
Dsys_ctrl.c83 HWREG(PRCM_BASE + NONSECURE_OFFSET + PRCM_O_PDCTL1VIMS) = vimsPdMode; in SysCtrlIdle()
184 …HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) &= (~PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN & ~PRCM_SECDMACLKGR_D… in SysCtrlStandby()
185 HWREG(PRCM_BASE + PRCM_O_I2SCLKGR) &= ~PRCM_I2SCLKGR_AM_CLK_EN; in SysCtrlStandby()
196 HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) = vimsPdMode; in SysCtrlStandby()
Drfc.h408 return (HWREG(PRCM_BASE + PRCM_O_PDCTL1RFC) | in RFCGetPowerDomainStatus()
409 HWREG(PRCM_BASE + PRCM_O_PDSTAT0RFC)); in RFCGetPowerDomainStatus()
Dchipinfo.c69 return ((ProtocolBitVector_t)( HWREG( PRCM_BASE + 0x1D4 ) & 0x0E )); in ChipInfo_GetSupportedProtocol_BV()
Dsetup.c190 HWREG( PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0; in SetupTrimDevice()
Dpka.c527 uint32_t secdmaclkgr = HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR); in PKAClearPkaRam()
533 HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr; in PKAClearPkaRam()
539 HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr & (~PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N); in PKAClearPkaRam()
/hal_ti-latest/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/
Dprcm.c186 HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor; in PRCMInfClockConfigureSet()
190 HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor; in PRCMInfClockConfigureSet()
194 HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor; in PRCMInfClockConfigureSet()
220 ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR); in PRCMInfClockConfigureGet()
224 ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS); in PRCMInfClockConfigureGet()
228 ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS); in PRCMInfClockConfigureGet()
314 HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; in PRCMAudioClockConfigSet()
315 HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; in PRCMAudioClockConfigSet()
316 HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; in PRCMAudioClockConfigSet()
319 ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | in PRCMAudioClockConfigSet()
[all …]
Dprcm.h335 HWREG(PRCM_BASE + PRCM_O_VDCTL) = ui32Enable; in PRCMMcuUldoConfigure()
374 HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV ) = clkDiv; in PRCMGPTimerClockDivisionSet()
400 return ( HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV )); in PRCMGPTimerClockDivisionGet()
417 HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 1; in PRCMAudioClockEnable()
433 HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 0; in PRCMAudioClockDisable()
609 return ((HWREG(PRCM_BASE + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ? in PRCMLoadGet()
643 HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = PRCM_RFCCLKG_CLK_EN; in PRCMDomainEnable()
647 HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = PRCM_VIMSCLKG_CLK_EN_M; in PRCMDomainEnable()
682 HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = 0x0; in PRCMDomainDisable()
686 HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = 0x0; in PRCMDomainDisable()
[all …]
Dsys_ctrl.c86 HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) = vimsPdMode; in SysCtrlIdle()
180 …HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) &= (~PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN & ~PRCM_SECDMACLKGR_D… in SysCtrlStandby()
181 HWREG(PRCM_BASE + PRCM_O_I2SCLKGR) &= ~PRCM_I2SCLKGR_AM_CLK_EN; in SysCtrlStandby()
192 HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) = vimsPdMode; in SysCtrlStandby()
Dchipinfo.c70 return ((ProtocolBitVector_t)( HWREG( PRCM_BASE + 0x1D4 ) & 0x0E )); in ChipInfo_GetSupportedProtocol_BV()
Dsetup.c188 HWREG( PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0; in SetupTrimDevice()
Dpka.c525 uint32_t secdmaclkgr = HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR); in PKAClearPkaRam()
531 HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr; in PKAClearPkaRam()
537 HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr & (~PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N); in PKAClearPkaRam()
/hal_ti-latest/simplelink/source/ti/drivers/power/
DPowerCC26X2.c340 HWREG(PRCM_BASE + PRCM_O_OSCIMSC) = 0; in Power_init()
368 HWREG(PRCM_BASE + PRCM_O_OSCIMSC) |= PRCM_OSCIMSC_LFSRCDONEIM_M; in Power_init()
401 HWREG(PRCM_BASE + PRCM_O_OSCIMSC) |= PRCM_OSCIMSC_LFSRCDONEIM_M; in Power_init()
1164 uint32_t rawStatus = HWREG(PRCM_BASE + PRCM_O_OSCRIS); in oscillatorISR()
1165 uint32_t intStatusMask = HWREG(PRCM_BASE + PRCM_O_OSCIMSC); in oscillatorISR()
1168 HWREG(PRCM_BASE + PRCM_O_OSCIMSC) = intStatusMask & ~rawStatus; in oscillatorISR()
1191 HWREG(PRCM_BASE + PRCM_O_OSCICR) = intStatusMask & rawStatus; in oscillatorISR()
1433 HWREG(PRCM_BASE + PRCM_O_OSCICR) = PRCM_OSCICR_HFSRCPENDC_M; in configureXOSCHF()
1436 HWREG(PRCM_BASE + PRCM_O_OSCIMSC) |= PRCM_OSCIMSC_HFSRCPENDIM_M; in configureXOSCHF()
1497 uint32_t oscMask = HWREG(PRCM_BASE + PRCM_O_OSCIMSC); in configureXOSCHF()
[all …]
/hal_ti-latest/simplelink/source/ti/devices/cc13x2x7_cc26x2x7/inc/
Dhw_memmap.h78 #define PRCM_BASE 0x40082000 // PRCM macro
/hal_ti-latest/simplelink/source/ti/devices/cc13x2_cc26x2/inc/
Dhw_memmap.h78 #define PRCM_BASE 0x40082000 // PRCM macro
/hal_ti-latest/simplelink/source/ti/drivers/rf/
DRFCC26X2_multiMode.c824 if (HWREG(PRCM_BASE + PRCM_O_PDSTAT0) & PRCM_PDSTAT0_RFC_ON) in RF_ratIsRunning()
3058 HWREG(PRCM_BASE + PRCM_O_RFCMODESEL) = RF_currClient->clientConfig.pRfMode->rfMode; in RF_fsmPowerUpState()
3284 HWREG(PRCM_BASE + PRCM_O_RFCBITS) |= RF_BOOT1; in RF_fsmActiveState()
3664 HWREG(PRCM_BASE + PRCM_O_RFCBITS) = RF_BOOT0; in RF_init()
4436 uint32_t availableRfModes = HWREG(PRCM_BASE + PRCM_O_RFCMODEHWOPT); in RF_open()