1 /****************************************************************************** 2 * Filename: hw_pmctl_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_PMCTL_H__ 34 #define __HW_PMCTL_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // PMCTL component 40 // 41 //***************************************************************************** 42 // Description Register. 43 #define PMCTL_O_DESC 0x00000000U 44 45 // Extended Description Register. 46 #define PMCTL_O_DESCEX 0x00000004U 47 48 // Shutdown Register. 49 #define PMCTL_O_SHTDWN 0x00000008U 50 51 // Sleep Control Register. 52 #define PMCTL_O_SLPCTL 0x0000000CU 53 54 // Wakeup Status Register 55 #define PMCTL_O_WUSTA 0x00000010U 56 57 // VDDR Control Register. 58 #define PMCTL_O_VDDRCTL 0x00000014U 59 60 // Internal. Only to be used through TI provided API. 61 #define PMCTL_O_SYSFSET 0x00000020U 62 63 // Internal. Only to be used through TI provided API. 64 #define PMCTL_O_SYSFCLR 0x00000024U 65 66 // Internal. Only to be used through TI provided API. 67 #define PMCTL_O_SYSFSTA 0x00000028U 68 69 // Reset Control Register. 70 #define PMCTL_O_RSTCTL 0x0000002CU 71 72 // Reset Status. 73 #define PMCTL_O_RSTSTA 0x00000030U 74 75 // Internal. Only to be used through TI provided API. 76 #define PMCTL_O_BOOTSTA 0x00000034U 77 78 // AON Register Status 1. 79 #define PMCTL_O_AONRSTA1 0x0000003CU 80 81 // AON Register Set 1. 82 #define PMCTL_O_AONRSET1 0x00000040U 83 84 // AON Register Clear 1. 85 #define PMCTL_O_AONRCLR1 0x00000044U 86 87 // Internal. Only to be used through TI provided API. 88 #define PMCTL_O_ETPP 0x00000064U 89 90 // Internal. Only to be used through TI provided API. 91 #define PMCTL_O_RETCFG0 0x0000007CU 92 93 // Internal. Only to be used through TI provided API. 94 #define PMCTL_O_RETCFG1 0x00000080U 95 96 // Internal. Only to be used through TI provided API. 97 #define PMCTL_O_RETCFG2 0x00000084U 98 99 // Internal. Only to be used through TI provided API. 100 #define PMCTL_O_RETCFG3 0x00000088U 101 102 // Internal. Only to be used through TI provided API. 103 #define PMCTL_O_RETCFG4 0x0000008CU 104 105 // Internal. Only to be used through TI provided API. 106 #define PMCTL_O_RETCFG5 0x00000090U 107 108 // Internal. Only to be used through TI provided API. 109 #define PMCTL_O_RETCFG6 0x00000094U 110 111 // Internal. Only to be used through TI provided API. 112 #define PMCTL_O_RETCFG7 0x00000098U 113 114 //***************************************************************************** 115 // 116 // Register: PMCTL_O_DESC 117 // 118 //***************************************************************************** 119 // Field: [31:16] MODID 120 // 121 // Module identifier used to uniquely identify this IP. 122 #define PMCTL_DESC_MODID_W 16U 123 #define PMCTL_DESC_MODID_M 0xFFFF0000U 124 #define PMCTL_DESC_MODID_S 16U 125 126 // Field: [15:12] STDIPOFF 127 // 128 // Standard IP MMR block offset. Standard IP MMRs are the set of from 129 // aggregated IRQ registers till DTB. 130 // 131 // 0: Standard IP MMRs do not exist 132 // 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP 133 // address) 134 #define PMCTL_DESC_STDIPOFF_W 4U 135 #define PMCTL_DESC_STDIPOFF_M 0x0000F000U 136 #define PMCTL_DESC_STDIPOFF_S 12U 137 138 // Field: [11:8] INSTIDX 139 // 140 // IP Instance ID number. If multiple instances of IP exist in the device, this 141 // field can identify the instance number (0-15). 142 #define PMCTL_DESC_INSTIDX_W 4U 143 #define PMCTL_DESC_INSTIDX_M 0x00000F00U 144 #define PMCTL_DESC_INSTIDX_S 8U 145 146 // Field: [7:4] MAJREV 147 // 148 // Major revision of IP (0-15). 149 #define PMCTL_DESC_MAJREV_W 4U 150 #define PMCTL_DESC_MAJREV_M 0x000000F0U 151 #define PMCTL_DESC_MAJREV_S 4U 152 153 // Field: [3:0] MINREV 154 // 155 // Minor revision of IP (0-15). 156 #define PMCTL_DESC_MINREV_W 4U 157 #define PMCTL_DESC_MINREV_M 0x0000000FU 158 #define PMCTL_DESC_MINREV_S 0U 159 160 //***************************************************************************** 161 // 162 // Register: PMCTL_O_DESCEX 163 // 164 //***************************************************************************** 165 // Field: [31:30] FLASHSZ 166 // 167 // System flash availability 168 // ENUMs: 169 // SZ3 Flash size set to level 3 (Max size) 170 // SZ2 Flash size set to level 2 171 // SZ1 Flash size set to level 1 172 // SZ0 Flash size set to level 0 (Min size) 173 #define PMCTL_DESCEX_FLASHSZ_W 2U 174 #define PMCTL_DESCEX_FLASHSZ_M 0xC0000000U 175 #define PMCTL_DESCEX_FLASHSZ_S 30U 176 #define PMCTL_DESCEX_FLASHSZ_SZ3 0xC0000000U 177 #define PMCTL_DESCEX_FLASHSZ_SZ2 0x80000000U 178 #define PMCTL_DESCEX_FLASHSZ_SZ1 0x40000000U 179 #define PMCTL_DESCEX_FLASHSZ_SZ0 0x00000000U 180 181 // Field: [29:28] SRAMSZ 182 // 183 // System SRAM availability 184 // ENUMs: 185 // SZ3 SRAM size set to level 3 (Max size) 186 // SZ2 SRAM size set to level 2 187 // SZ1 SRAM size set to level 1 188 // SZ0 SRAM size set to level 0 (Min size) 189 #define PMCTL_DESCEX_SRAMSZ_W 2U 190 #define PMCTL_DESCEX_SRAMSZ_M 0x30000000U 191 #define PMCTL_DESCEX_SRAMSZ_S 28U 192 #define PMCTL_DESCEX_SRAMSZ_SZ3 0x30000000U 193 #define PMCTL_DESCEX_SRAMSZ_SZ2 0x20000000U 194 #define PMCTL_DESCEX_SRAMSZ_SZ1 0x10000000U 195 #define PMCTL_DESCEX_SRAMSZ_SZ0 0x00000000U 196 197 // Field: [27] TSD 198 // 199 // TSD (thermal shutdown) IP status on device 200 // ENUMs: 201 // IP_AVAIL IP is available 202 // IP_UNAVAIL IP is unavailable 203 #define PMCTL_DESCEX_TSD 0x08000000U 204 #define PMCTL_DESCEX_TSD_M 0x08000000U 205 #define PMCTL_DESCEX_TSD_S 27U 206 #define PMCTL_DESCEX_TSD_IP_AVAIL 0x08000000U 207 #define PMCTL_DESCEX_TSD_IP_UNAVAIL 0x00000000U 208 209 // Field: [26] LPCMP 210 // 211 // LPCMP (low power comparator) IP status on device 212 // ENUMs: 213 // IP_AVAIL IP is available 214 // IP_UNAVAIL IP is unavailable 215 #define PMCTL_DESCEX_LPCMP 0x04000000U 216 #define PMCTL_DESCEX_LPCMP_M 0x04000000U 217 #define PMCTL_DESCEX_LPCMP_S 26U 218 #define PMCTL_DESCEX_LPCMP_IP_AVAIL 0x04000000U 219 #define PMCTL_DESCEX_LPCMP_IP_UNAVAIL 0x00000000U 220 221 //***************************************************************************** 222 // 223 // Register: PMCTL_O_SHTDWN 224 // 225 //***************************************************************************** 226 // Field: [15:0] KEY 227 // 228 // Setting a valid key will trigger the device to enter SHUTDOWN mode. 229 // ENUMs: 230 // VALID This is the only valid key value that will trigger 231 // SHUTDOWN mode. 232 // All other values are 233 // invalid and will have no effect. 234 #define PMCTL_SHTDWN_KEY_W 16U 235 #define PMCTL_SHTDWN_KEY_M 0x0000FFFFU 236 #define PMCTL_SHTDWN_KEY_S 0U 237 #define PMCTL_SHTDWN_KEY_VALID 0x0000A5A5U 238 239 //***************************************************************************** 240 // 241 // Register: PMCTL_O_SLPCTL 242 // 243 //***************************************************************************** 244 // Field: [0] SLPN 245 // 246 // The boot code will set this bit field and disable sleep mode, automatically 247 // unless waking up from a SHUTDOWN RSTSTA.SDDET is set. 248 // Application software must reconfigure the state for all IO's before setting 249 // this bit field upon waking up from a SHUTDOWN to avoid glitches on pins. 250 // ENUMs: 251 // DIS I/O pad sleep mode is disabled 252 // EN I/O pad sleep mode is enabled 253 #define PMCTL_SLPCTL_SLPN 0x00000001U 254 #define PMCTL_SLPCTL_SLPN_M 0x00000001U 255 #define PMCTL_SLPCTL_SLPN_S 0U 256 #define PMCTL_SLPCTL_SLPN_DIS 0x00000001U 257 #define PMCTL_SLPCTL_SLPN_EN 0x00000000U 258 259 //***************************************************************************** 260 // 261 // Register: PMCTL_O_WUSTA 262 // 263 //***************************************************************************** 264 // Field: [1:0] SRC 265 // 266 // This field shows the device wakeup source. 267 // ENUMs: 268 // STBY Wakeup from STANDBY mode. 269 // RST_SHTDWN Wakeup from system reset / SHUTDOWN mode. 270 // See RSTSTA for more 271 // status information. 272 #define PMCTL_WUSTA_SRC_W 2U 273 #define PMCTL_WUSTA_SRC_M 0x00000003U 274 #define PMCTL_WUSTA_SRC_S 0U 275 #define PMCTL_WUSTA_SRC_STBY 0x00000002U 276 #define PMCTL_WUSTA_SRC_RST_SHTDWN 0x00000001U 277 278 //***************************************************************************** 279 // 280 // Register: PMCTL_O_VDDRCTL 281 // 282 //***************************************************************************** 283 // Field: [1] STBY 284 // 285 // Select between continuous or duty-cycled VDDR regulation in STANDBY mode. 286 // ENUMs: 287 // PSUEDO Continuous VDDR regulation in STANDBY mode. 288 // NORMAL Duty-cycled VDDR regulation in STANDBY mode. 289 #define PMCTL_VDDRCTL_STBY 0x00000002U 290 #define PMCTL_VDDRCTL_STBY_M 0x00000002U 291 #define PMCTL_VDDRCTL_STBY_S 1U 292 #define PMCTL_VDDRCTL_STBY_PSUEDO 0x00000002U 293 #define PMCTL_VDDRCTL_STBY_NORMAL 0x00000000U 294 295 // Field: [0] SELECT 296 // 297 // Select between GLDO and DCDC as VDDR regulator (in ACTIVE, IDLE and STANDBY 298 // mode). 299 // ENUMs: 300 // DCDC DCDC enabled for regulation of VDDR voltage 301 // GLDO GLDO enabled for regulation of VDDR voltage 302 #define PMCTL_VDDRCTL_SELECT 0x00000001U 303 #define PMCTL_VDDRCTL_SELECT_M 0x00000001U 304 #define PMCTL_VDDRCTL_SELECT_S 0U 305 #define PMCTL_VDDRCTL_SELECT_DCDC 0x00000001U 306 #define PMCTL_VDDRCTL_SELECT_GLDO 0x00000000U 307 308 //***************************************************************************** 309 // 310 // Register: PMCTL_O_SYSFSET 311 // 312 //***************************************************************************** 313 // Field: [2] FLAG2 314 // 315 // Internal. Only to be used through TI provided API. 316 // ENUMs: 317 // SET Internal. Only to be used through TI provided API. 318 // NOEFF Internal. Only to be used through TI provided API. 319 #define PMCTL_SYSFSET_FLAG2 0x00000004U 320 #define PMCTL_SYSFSET_FLAG2_M 0x00000004U 321 #define PMCTL_SYSFSET_FLAG2_S 2U 322 #define PMCTL_SYSFSET_FLAG2_SET 0x00000004U 323 #define PMCTL_SYSFSET_FLAG2_NOEFF 0x00000000U 324 325 // Field: [1] FLAG1 326 // 327 // Internal. Only to be used through TI provided API. 328 // ENUMs: 329 // SET Internal. Only to be used through TI provided API. 330 // NOEFF Internal. Only to be used through TI provided API. 331 #define PMCTL_SYSFSET_FLAG1 0x00000002U 332 #define PMCTL_SYSFSET_FLAG1_M 0x00000002U 333 #define PMCTL_SYSFSET_FLAG1_S 1U 334 #define PMCTL_SYSFSET_FLAG1_SET 0x00000002U 335 #define PMCTL_SYSFSET_FLAG1_NOEFF 0x00000000U 336 337 // Field: [0] FLAG0 338 // 339 // Internal. Only to be used through TI provided API. 340 // ENUMs: 341 // SET Internal. Only to be used through TI provided API. 342 // NOEFF Internal. Only to be used through TI provided API. 343 #define PMCTL_SYSFSET_FLAG0 0x00000001U 344 #define PMCTL_SYSFSET_FLAG0_M 0x00000001U 345 #define PMCTL_SYSFSET_FLAG0_S 0U 346 #define PMCTL_SYSFSET_FLAG0_SET 0x00000001U 347 #define PMCTL_SYSFSET_FLAG0_NOEFF 0x00000000U 348 349 //***************************************************************************** 350 // 351 // Register: PMCTL_O_SYSFCLR 352 // 353 //***************************************************************************** 354 // Field: [2] FLAG2 355 // 356 // Internal. Only to be used through TI provided API. 357 // ENUMs: 358 // CLR Internal. Only to be used through TI provided API. 359 // NOEFF Internal. Only to be used through TI provided API. 360 #define PMCTL_SYSFCLR_FLAG2 0x00000004U 361 #define PMCTL_SYSFCLR_FLAG2_M 0x00000004U 362 #define PMCTL_SYSFCLR_FLAG2_S 2U 363 #define PMCTL_SYSFCLR_FLAG2_CLR 0x00000004U 364 #define PMCTL_SYSFCLR_FLAG2_NOEFF 0x00000000U 365 366 // Field: [1] FLAG1 367 // 368 // Internal. Only to be used through TI provided API. 369 // ENUMs: 370 // CLR Internal. Only to be used through TI provided API. 371 // NOEFF Internal. Only to be used through TI provided API. 372 #define PMCTL_SYSFCLR_FLAG1 0x00000002U 373 #define PMCTL_SYSFCLR_FLAG1_M 0x00000002U 374 #define PMCTL_SYSFCLR_FLAG1_S 1U 375 #define PMCTL_SYSFCLR_FLAG1_CLR 0x00000002U 376 #define PMCTL_SYSFCLR_FLAG1_NOEFF 0x00000000U 377 378 // Field: [0] FLAG0 379 // 380 // Internal. Only to be used through TI provided API. 381 // ENUMs: 382 // CLR Internal. Only to be used through TI provided API. 383 // NOEFF Internal. Only to be used through TI provided API. 384 #define PMCTL_SYSFCLR_FLAG0 0x00000001U 385 #define PMCTL_SYSFCLR_FLAG0_M 0x00000001U 386 #define PMCTL_SYSFCLR_FLAG0_S 0U 387 #define PMCTL_SYSFCLR_FLAG0_CLR 0x00000001U 388 #define PMCTL_SYSFCLR_FLAG0_NOEFF 0x00000000U 389 390 //***************************************************************************** 391 // 392 // Register: PMCTL_O_SYSFSTA 393 // 394 //***************************************************************************** 395 // Field: [2] FLAG2 396 // 397 // Internal. Only to be used through TI provided API. 398 // ENUMs: 399 // VAL1 Internal. Only to be used through TI provided API. 400 // VAL0 Internal. Only to be used through TI provided API. 401 #define PMCTL_SYSFSTA_FLAG2 0x00000004U 402 #define PMCTL_SYSFSTA_FLAG2_M 0x00000004U 403 #define PMCTL_SYSFSTA_FLAG2_S 2U 404 #define PMCTL_SYSFSTA_FLAG2_VAL1 0x00000004U 405 #define PMCTL_SYSFSTA_FLAG2_VAL0 0x00000000U 406 407 // Field: [1] FLAG1 408 // 409 // Internal. Only to be used through TI provided API. 410 // ENUMs: 411 // VAL1 Internal. Only to be used through TI provided API. 412 #define PMCTL_SYSFSTA_FLAG1 0x00000002U 413 #define PMCTL_SYSFSTA_FLAG1_M 0x00000002U 414 #define PMCTL_SYSFSTA_FLAG1_S 1U 415 #define PMCTL_SYSFSTA_FLAG1_VAL1 0x00000002U 416 417 // Field: [0] FLAG0 418 // 419 // Internal. Only to be used through TI provided API. 420 // ENUMs: 421 // VAL1 Internal. Only to be used through TI provided API. 422 // VAL0 Internal. Only to be used through TI provided API. 423 #define PMCTL_SYSFSTA_FLAG0 0x00000001U 424 #define PMCTL_SYSFSTA_FLAG0_M 0x00000001U 425 #define PMCTL_SYSFSTA_FLAG0_S 0U 426 #define PMCTL_SYSFSTA_FLAG0_VAL1 0x00000001U 427 #define PMCTL_SYSFSTA_FLAG0_VAL0 0x00000000U 428 429 //***************************************************************************** 430 // 431 // Register: PMCTL_O_RSTCTL 432 // 433 //***************************************************************************** 434 // Field: [2] LFLOSS 435 // 436 // LF clock loss reset enable. 437 // Trigger system reset when LF clock loss is detected, which reset the entire 438 // device and causes a reboot of the system. 439 // The system reset event is captured as RSTSTA.RESETSRC set to SYSRESET and 440 // RSTSTA.SYSSRC set to LFLOSSEV. 441 // ENUMs: 442 // ARMED LF clock loss detection will trigger a system 443 // reset. 444 // DISARMED LF clock loss detection will not trigger a system 445 // reset. 446 #define PMCTL_RSTCTL_LFLOSS 0x00000004U 447 #define PMCTL_RSTCTL_LFLOSS_M 0x00000004U 448 #define PMCTL_RSTCTL_LFLOSS_S 2U 449 #define PMCTL_RSTCTL_LFLOSS_ARMED 0x00000004U 450 #define PMCTL_RSTCTL_LFLOSS_DISARMED 0x00000000U 451 452 // Field: [1] TSDEN 453 // 454 // TSD (Thermal Shutdown) enable. 455 // TSD will trigger an immediate system reset, which reset the entire device 456 // and causes a reboot of the system. 457 // The device will be in reset until released by the TSD IP. 458 // The system reset event is captured as RSTSTA.TSDEV flag set. 459 // ENUMs: 460 // EN Temperature shutdown comparator enable. 461 // Note: If TSD IP not 462 // present, see DESCEX.TSD, enable will have no 463 // effect. 464 // NOEFF No effect 465 #define PMCTL_RSTCTL_TSDEN 0x00000002U 466 #define PMCTL_RSTCTL_TSDEN_M 0x00000002U 467 #define PMCTL_RSTCTL_TSDEN_S 1U 468 #define PMCTL_RSTCTL_TSDEN_EN 0x00000002U 469 #define PMCTL_RSTCTL_TSDEN_NOEFF 0x00000000U 470 471 // Field: [0] SYSRST 472 // 473 // Trigger system reset, which will reset the entire device and causes a reboot 474 // of the system. 475 // The system reset event is captured as RSTSTA.RESETSRC set to SYSRESET and 476 // RSTSTA.SYSSRC set to SYSRSTEV. 477 // ENUMs: 478 // SET Trigger a system reset. 479 // NOEFF No effect 480 #define PMCTL_RSTCTL_SYSRST 0x00000001U 481 #define PMCTL_RSTCTL_SYSRST_M 0x00000001U 482 #define PMCTL_RSTCTL_SYSRST_S 0U 483 #define PMCTL_RSTCTL_SYSRST_SET 0x00000001U 484 #define PMCTL_RSTCTL_SYSRST_NOEFF 0x00000000U 485 486 //***************************************************************************** 487 // 488 // Register: PMCTL_O_RSTSTA 489 // 490 //***************************************************************************** 491 // Field: [17] SDDET 492 // 493 // Wakeup from SHUTDOWN flag. 494 // Note: This flag will be cleared when SLPCTL.SLPN is asserted. 495 // ENUMs: 496 // TRIG Wakeup from SHUTDOWN mode 497 // NO_TRIG Wakeup from SHUTDOWN mode not triggered 498 #define PMCTL_RSTSTA_SDDET 0x00020000U 499 #define PMCTL_RSTSTA_SDDET_M 0x00020000U 500 #define PMCTL_RSTSTA_SDDET_S 17U 501 #define PMCTL_RSTSTA_SDDET_TRIG 0x00020000U 502 #define PMCTL_RSTSTA_SDDET_NO_TRIG 0x00000000U 503 504 // Field: [16] IOWUSD 505 // 506 // Wakeup from SHUTDOWN on an I/O event flag. 507 // Note: This flag will be cleared when SLPCTL.SLPN is asserted. 508 // ENUMs: 509 // TRIG Wakeup from SHUTDOWN triggered by an I/O event. 510 // NO_TRIG Wakeup from SHUTDOWN not triggered by an I/O 511 // event. 512 #define PMCTL_RSTSTA_IOWUSD 0x00010000U 513 #define PMCTL_RSTSTA_IOWUSD_M 0x00010000U 514 #define PMCTL_RSTSTA_IOWUSD_S 16U 515 #define PMCTL_RSTSTA_IOWUSD_TRIG 0x00010000U 516 #define PMCTL_RSTSTA_IOWUSD_NO_TRIG 0x00000000U 517 518 // Field: [7:4] SYSSRC 519 // 520 // Shows which reset event that triggered SYSRESET in RESETSRC 521 // ENUMs: 522 // DERREV Digital Error reset event 523 // AERREV Analog Error reset event 524 // AFSMEV Analog FSM timeout event 525 // SWDRSTEV Serial Wire Debug reset event 526 // SYSRSTEV System reset event 527 // WDTEV Watchdog timeout event 528 // LOCKUPEV CPU LOCKUP event 529 // CPURSTEV CPU reset event 530 // LFLOSSEV LF clock loss event 531 #define PMCTL_RSTSTA_SYSSRC_W 4U 532 #define PMCTL_RSTSTA_SYSSRC_M 0x000000F0U 533 #define PMCTL_RSTSTA_SYSSRC_S 4U 534 #define PMCTL_RSTSTA_SYSSRC_DERREV 0x000000F0U 535 #define PMCTL_RSTSTA_SYSSRC_AERREV 0x000000E0U 536 #define PMCTL_RSTSTA_SYSSRC_AFSMEV 0x00000060U 537 #define PMCTL_RSTSTA_SYSSRC_SWDRSTEV 0x00000050U 538 #define PMCTL_RSTSTA_SYSSRC_SYSRSTEV 0x00000040U 539 #define PMCTL_RSTSTA_SYSSRC_WDTEV 0x00000030U 540 #define PMCTL_RSTSTA_SYSSRC_LOCKUPEV 0x00000020U 541 #define PMCTL_RSTSTA_SYSSRC_CPURSTEV 0x00000010U 542 #define PMCTL_RSTSTA_SYSSRC_LFLOSSEV 0x00000000U 543 544 // Field: [3] TSDEV 545 // 546 // System reset triggered by TSD event 547 // ENUMs: 548 // TRIG System reset triggered by TSD event 549 // NO_TRIG TSD event not triggered 550 #define PMCTL_RSTSTA_TSDEV 0x00000008U 551 #define PMCTL_RSTSTA_TSDEV_M 0x00000008U 552 #define PMCTL_RSTSTA_TSDEV_S 3U 553 #define PMCTL_RSTSTA_TSDEV_TRIG 0x00000008U 554 #define PMCTL_RSTSTA_TSDEV_NO_TRIG 0x00000000U 555 556 // Field: [2:0] RESETSRC 557 // 558 // Shows the root cause of the last system reset. More than one reported reset 559 // source can have been active during the last system reset, but only the root 560 // cause is reported. 561 // If reset cause is SYSRESET or PINRESET, the other reset flags must be read 562 // to determine actual root cause. 563 // ENUMs: 564 // SYSRESET Digital system reset. Actual root cause is given 565 // by SYSSRC. 566 // VDDRLOSS Brown out detect on VDDR 567 // VDDSLOSS Brown out detect on VDDS 568 // PINRESET Reset pin. TSD will also trigger a pin reset, so 569 // actual root cause is given by TSDEV reset flag 570 // status. 571 // PWRON Power on reset 572 #define PMCTL_RSTSTA_RESETSRC_W 3U 573 #define PMCTL_RSTSTA_RESETSRC_M 0x00000007U 574 #define PMCTL_RSTSTA_RESETSRC_S 0U 575 #define PMCTL_RSTSTA_RESETSRC_SYSRESET 0x00000006U 576 #define PMCTL_RSTSTA_RESETSRC_VDDRLOSS 0x00000004U 577 #define PMCTL_RSTSTA_RESETSRC_VDDSLOSS 0x00000002U 578 #define PMCTL_RSTSTA_RESETSRC_PINRESET 0x00000001U 579 #define PMCTL_RSTSTA_RESETSRC_PWRON 0x00000000U 580 581 //***************************************************************************** 582 // 583 // Register: PMCTL_O_BOOTSTA 584 // 585 //***************************************************************************** 586 // Field: [7:0] FLAG 587 // 588 // Internal. Only to be used through TI provided API. 589 // ENUMs: 590 // APP_FAULT_HANDLER Internal. Only to be used through TI provided API. 591 // APP_FAIL_APPTRANSFER Internal. Only to be used through TI provided API. 592 // APP_FAIL_NOAPP Internal. Only to be used through TI provided API. 593 // APP_WAITLOOP_DBGPROBE Internal. Only to be used through TI provided API. 594 // MODE_APP Internal. Only to be used through TI provided API. 595 // BLDR_FAULT_HANDLER Internal. Only to be used through TI provided API. 596 // BLDR_FAIL_APPTRANSFER Internal. Only to be used through TI provided API. 597 // BLDR_FAIL_EXECUTION_CONTEXTInternal. Only to be used through TI provided 598 // API. 599 // BLDR_CMD_PROCESSING Internal. Only to be used through TI provided API. 600 // BLDR_CMD_IDLE Internal. Only to be used through TI provided API. 601 // BLDR_STARTED Internal. Only to be used through TI provided API. 602 // BLDR_WAITLOOP_DBGPROBE Internal. Only to be used through TI provided API. 603 // MODE_BLDR Internal. Only to be used through TI provided API. 604 // BOOT_FAULT_HANDLER Internal. Only to be used through TI provided API. 605 // BOOT_FAIL_SRAM_REPAIR Internal. Only to be used through TI provided API. 606 // BOOT_WAITLOOP_DBGPROBE Internal. Only to be used through TI provided API. 607 // BOOT_EXITED_SACI Internal. Only to be used through TI provided API. 608 // BOOT_WAIT_SWD_DISCONNECT Internal. Only to be used through TI provided API. 609 // BOOT_ENTERED_SACI Internal. Only to be used through TI provided API. 610 // BOOT_GENERAL_TRIMS Internal. Only to be used through TI provided API. 611 // BOOT_SRAM_REP_DONE Internal. Only to be used through TI provided API. 612 // BOOT_COLD_BOOT Internal. Only to be used through TI provided API. 613 // BOOT_RESET Internal. Only to be used through TI provided API. 614 #define PMCTL_BOOTSTA_FLAG_W 8U 615 #define PMCTL_BOOTSTA_FLAG_M 0x000000FFU 616 #define PMCTL_BOOTSTA_FLAG_S 0U 617 #define PMCTL_BOOTSTA_FLAG_APP_FAULT_HANDLER 0x000000FFU 618 #define PMCTL_BOOTSTA_FLAG_APP_FAIL_APPTRANSFER 0x000000FEU 619 #define PMCTL_BOOTSTA_FLAG_APP_FAIL_NOAPP 0x000000FDU 620 #define PMCTL_BOOTSTA_FLAG_APP_WAITLOOP_DBGPROBE 0x000000C1U 621 #define PMCTL_BOOTSTA_FLAG_MODE_APP 0x000000C0U 622 #define PMCTL_BOOTSTA_FLAG_BLDR_FAULT_HANDLER 0x000000BFU 623 #define PMCTL_BOOTSTA_FLAG_BLDR_FAIL_APPTRANSFER 0x000000BEU 624 #define PMCTL_BOOTSTA_FLAG_BLDR_FAIL_EXECUTION_CONTEXT 0x000000BDU 625 #define PMCTL_BOOTSTA_FLAG_BLDR_CMD_PROCESSING 0x000000BCU 626 #define PMCTL_BOOTSTA_FLAG_BLDR_CMD_IDLE 0x000000BBU 627 #define PMCTL_BOOTSTA_FLAG_BLDR_STARTED 0x000000BAU 628 #define PMCTL_BOOTSTA_FLAG_BLDR_WAITLOOP_DBGPROBE 0x00000081U 629 #define PMCTL_BOOTSTA_FLAG_MODE_BLDR 0x00000080U 630 #define PMCTL_BOOTSTA_FLAG_BOOT_FAULT_HANDLER 0x0000003FU 631 #define PMCTL_BOOTSTA_FLAG_BOOT_FAIL_SRAM_REPAIR 0x0000003EU 632 #define PMCTL_BOOTSTA_FLAG_BOOT_WAITLOOP_DBGPROBE 0x00000038U 633 #define PMCTL_BOOTSTA_FLAG_BOOT_EXITED_SACI 0x00000037U 634 #define PMCTL_BOOTSTA_FLAG_BOOT_WAIT_SWD_DISCONNECT 0x00000036U 635 #define PMCTL_BOOTSTA_FLAG_BOOT_ENTERED_SACI 0x00000020U 636 #define PMCTL_BOOTSTA_FLAG_BOOT_GENERAL_TRIMS 0x00000003U 637 #define PMCTL_BOOTSTA_FLAG_BOOT_SRAM_REP_DONE 0x00000002U 638 #define PMCTL_BOOTSTA_FLAG_BOOT_COLD_BOOT 0x00000001U 639 #define PMCTL_BOOTSTA_FLAG_BOOT_RESET 0x00000000U 640 641 //***************************************************************************** 642 // 643 // Register: PMCTL_O_AONRSTA1 644 // 645 //***************************************************************************** 646 // Field: [17:0] FLAG 647 // 648 // State of the AON register flags 649 #define PMCTL_AONRSTA1_FLAG_W 18U 650 #define PMCTL_AONRSTA1_FLAG_M 0x0003FFFFU 651 #define PMCTL_AONRSTA1_FLAG_S 0U 652 653 //***************************************************************************** 654 // 655 // Register: PMCTL_O_AONRSET1 656 // 657 //***************************************************************************** 658 // Field: [17:0] FLAG 659 // 660 // Write 1 to set AONRSTA1.FLAG 661 // ENUMs: 662 // ALL_SET Set all flags 663 // NOEFF No flags changed status 664 #define PMCTL_AONRSET1_FLAG_W 18U 665 #define PMCTL_AONRSET1_FLAG_M 0x0003FFFFU 666 #define PMCTL_AONRSET1_FLAG_S 0U 667 #define PMCTL_AONRSET1_FLAG_ALL_SET 0x0003FFFFU 668 #define PMCTL_AONRSET1_FLAG_NOEFF 0x00000000U 669 670 //***************************************************************************** 671 // 672 // Register: PMCTL_O_AONRCLR1 673 // 674 //***************************************************************************** 675 // Field: [17:0] FLAG 676 // 677 // Write 1 to clear AONRSTA1.FLAG 678 // ENUMs: 679 // ALL_CLR Clear all flags 680 // NOEFF No flags changed status 681 #define PMCTL_AONRCLR1_FLAG_W 18U 682 #define PMCTL_AONRCLR1_FLAG_M 0x0003FFFFU 683 #define PMCTL_AONRCLR1_FLAG_S 0U 684 #define PMCTL_AONRCLR1_FLAG_ALL_CLR 0x0003FFFFU 685 #define PMCTL_AONRCLR1_FLAG_NOEFF 0x00000000U 686 687 //***************************************************************************** 688 // 689 // Register: PMCTL_O_ETPP 690 // 691 //***************************************************************************** 692 //***************************************************************************** 693 // 694 // Register: PMCTL_O_RETCFG0 695 // 696 //***************************************************************************** 697 // Field: [0] VAL 698 // 699 // Internal. Only to be used through TI provided API. 700 #define PMCTL_RETCFG0_VAL 0x00000001U 701 #define PMCTL_RETCFG0_VAL_M 0x00000001U 702 #define PMCTL_RETCFG0_VAL_S 0U 703 704 //***************************************************************************** 705 // 706 // Register: PMCTL_O_RETCFG1 707 // 708 //***************************************************************************** 709 // Field: [0] VAL 710 // 711 // Internal. Only to be used through TI provided API. 712 #define PMCTL_RETCFG1_VAL 0x00000001U 713 #define PMCTL_RETCFG1_VAL_M 0x00000001U 714 #define PMCTL_RETCFG1_VAL_S 0U 715 716 //***************************************************************************** 717 // 718 // Register: PMCTL_O_RETCFG2 719 // 720 //***************************************************************************** 721 // Field: [2:0] VAL 722 // 723 // Internal. Only to be used through TI provided API. 724 #define PMCTL_RETCFG2_VAL_W 3U 725 #define PMCTL_RETCFG2_VAL_M 0x00000007U 726 #define PMCTL_RETCFG2_VAL_S 0U 727 728 //***************************************************************************** 729 // 730 // Register: PMCTL_O_RETCFG3 731 // 732 //***************************************************************************** 733 //***************************************************************************** 734 // 735 // Register: PMCTL_O_RETCFG4 736 // 737 //***************************************************************************** 738 //***************************************************************************** 739 // 740 // Register: PMCTL_O_RETCFG5 741 // 742 //***************************************************************************** 743 //***************************************************************************** 744 // 745 // Register: PMCTL_O_RETCFG6 746 // 747 //***************************************************************************** 748 //***************************************************************************** 749 // 750 // Register: PMCTL_O_RETCFG7 751 // 752 //***************************************************************************** 753 754 #endif // __PMCTL__ 755
